Phase synchronization circuit and method therefor for a phase locked loop

• US 5,497,126 A
• Filed: 11/09/1993
• Issued: 03/05/1996
• Est. Priority Date: 11/09/1993
• Status: Expired due to Term

• Current Assignee: Quarterhill Inc. (f/k/a Wi-LAN Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Kosiec, Jeannie H., Gillig, Steven F.
• Primary Examiner(s): Pascal, Robert J.
• Assistant Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US08/149,259
• Time in Patent Office: 847 Days
• Field of Search: 331/25, 331/1 A, 331/14, 331/11, 331/16, 328/155, 455/260, 455/76, 455/113, 327/156, 327/157, 327/159, 375/374, 375/376
• US Class Current: 331/1.00A
• CPC Class Codes: H03L 3/00 Starting of generators
• CPC Class Codes: H03L 7/10 for assuring initial synchronisation or for broadening the capture range
• CPC Class Codes: H03L 7/101 using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop H03L7/113, H03L7/187 take precedence
• CPC Class Codes: H03L 7/107 using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

An improved phase synchronization circuit (301) and method therefor for a phase locked loop (300). Each of a divided reference frequency signal (206) and a feedback signal (209) is held in a predetermined state. The divided reference frequency signal (206) is enabled responsive to the phase of a reference frequency signal (115). A phase relationship between the reference frequency signal (115) and an output frequency signal (116 or 117) is determined. The feedback signal (209) is enabled responsive to enabling the divided reference frequency signal (206) and the determined phase relationship. The present invention advantageously provides a rapid and accurate phase synchronization for the PLL (300) with minimum additional hardware and without introducing phase error into the PLL (300).

Claims

1. A phase synchronization circuit for a phase locked loop (PLL) that generates an output frequency signal responsive to a reference frequency signal, the output frequency signal and the reference frequency signal are each characterized by frequency and phase, the frequency of the reference frequency signal is divided to produce a divided reference frequency signal, the output frequency signal is divided to produce a feedback signal, a phase error is indicative of a difference between the phase of the reference frequency signal and the phase of the output frequency signal, the PLL is operative to reduce the phase error responsive to a periodic indication of the phase error, the PLL has a first and a second state responsive to a request signal, an occurrence of the request signal is not synchronized in time with the periodic indication of the phase error, the phase synchronization circuit for the PLL comprising:

a PLL state control circuit coupled to receive the request signal, the periodic indication of the phase error, and a first reset signal, and operative to produce a set signal and a PLL state control signal;

a signal detector coupled to receive the request signal, the output frequency signal, the reference frequency signal, and the set signal, and operative to produce second and third reset signals;

a timing control circuit coupled to receive the second and third reset signals, and the set signal, and operative to produce first and second timing signals;

a reset circuit coupled to receive the request signal and the first and second timing signals and operative to produce the first reset signal; and

a logic circuit coupled to receive the first and second timing signals, the divided reference frequency signal, and the feedback signal, and operative to produce a synchronized divided reference frequency signal and a synchronized feedback signal.

2. A phase synchronization circuit according to claim 1 wherein the PLL state control signal controls the first and second states of the PLL.

3. A phase synchronization circuit according to claim 1 wherein the set signal prepares the signal detector to detect a first state of the request signal.

4. A phase synchronization circuit according to claim 1 wherein the set signal holds each of the first and second timing signals in a predetermined state, and wherein the second and third reset signals release the first and second timing signals, respectively, from their respective predetermined states.

5. A phase synchronization circuit according to claim 1 wherein the first reset signal prepares the PLL state control circuit to detect a second state of the request signal.

6. A phase synchronization circuit according to claim 1 wherein the first timing signal and the divided reference frequency signal are combined to produce the synchronized divided reference frequency signal, and wherein the second timing signal and the feedback signal are combined to produce the synchronized feedback signal.

7. In a phase locked loop (PLL) that generates an output frequency signal responsive to a reference frequency signal, the output frequency signal and the reference frequency signal are each characterized by frequency and phase, the output frequency signal has a higher frequency than the reference frequency signal, the frequency of the reference frequency signal is divided to produce a divided reference frequency signal, the frequency of the output frequency signal is divided to produce a feedback signal, the PLL having first and second states, a method for synchronizing the phase of the divided reference frequency signal and the phase of the feedback signal comprising the steps of:

holding each of the divided reference frequency signal and the feedback signal in a predetermined state;

enabling during the second state of the PLL, the divided reference frequency signal responsive to the phase of the reference frequency signal;

determining a phase relationship between the reference frequency signal and the output frequency signal; and

enabling the feedback signal responsive to enabling the divided reference frequency signal and the determined phase relationship.

8. In a phase locked loop (PLL) that generates an output frequency signal responsive to a reference frequency signal, the output frequency signal and the reference frequency signal are each characterized by frequency and phase, the output frequency signal has a higher frequency than the reference frequency signal, the frequency of the reference frequency signal is divided to produce a divided reference frequency signal, the frequency of the output frequency signal is divided to produce a feedback signal, a phase error is indicative of a difference between the phase of the reference frequency signal and the phase of the output frequency signal, the PLL having a first and a second state responsive to a request signal, an occurrence of the request signal is not synchronized in time with a periodic indication of the phase error, a method for synchronizing the phase of the divided reference frequency signal and the phase of the feedback signal comprising the steps of:

detecting the request signal having first and second states corresponding to first and second states of the PLL;

when the detected requested signal is in the first state, holding each of the divided reference frequency signal and the feedback signal in a predetermined state; and

when the detected requested signal is in the second state;

enabling the divided reference frequency signal responsive to the phase of the reference frequency signal;

determining a phase relationship between the reference frequency signal and the output frequency signal; and

enabling the feedback signal responsive to enabling the divided reference frequency signal and the determined phase relationship.

9. A radio frequency receiver includes a phase locked loop (PLL) frequency synthesizer operative to tune the radio frequency receiver to a radio frequency channel, the PLL frequency synthesizer includes a PLL capable of being enabled and disabled responsive to a request signal, the PLL generates an output frequency signal responsive to a reference frequency signal, the output frequency signal and the reference frequency signal are each characterized by frequency and phase, the frequency of the reference frequency signal is divided to produce a divided reference frequency signal, the output frequency signal is divided to produce a feedback signal, a phase error is indicative of a difference between the phase of the reference frequency signal and the phase of the output frequency signal, the PLL is operative to reduce the phase error responsive to a periodic indication of the phase error, an occurrence of the request signal is not synchronized in time with the periodic indication of the phase error, the radio frequency receiver comprising:

a receiver line up coupled to receive a radio frequency signal and operative to produce a received signal;

a processor coupled to receive the received signal and operative to produce the request signal responsive to the received signal; and

a phase synchronization circuit in the PLL comprising;

a PLL state control circuit coupled to receive the request signal, the periodic indication of the phase error, and a first reset signal, and operative to produce a set signal and a PLL state control signal;

a signal detector coupled to receive the request signal, the output frequency signal, the reference frequency signal, and the set signal, and operative to produce second and third reset signals;

a timing control circuit coupled to receive the second and third reset signals, and the set signal, and operative to produce first and second timing signals;

a reset circuit coupled to receive the request signal and the first and second timing signals and operative to produce the first reset signal; and

a logic circuit coupled to receive the first and second timing signals, the divided reference frequency signal, and the feedback signal, and operative to produce a synchronized divided reference frequency signal and a synchronized feedback signal.

10. A method of operating a radio frequency receiver including a phase locked loop (PLL) frequency synthesizer operative to tune the radio frequency receiver to a radio frequency channel, the PLL frequency synthesizer includes a PLL capable of being enabled and disabled responsive to a request signal, the PLL generates an output frequency signal responsive to a reference frequency signal, the output frequency signal has a higher frequency than the reference frequency signal, the output frequency signal and the reference frequency signal are each characterized by frequency and phase, the frequency of the reference frequency signal is divided to produce a divided reference frequency signal, the output frequency signal is divided to produce a feedback signal, a phase error is indicative of a difference between the phase of the reference frequency signal and the phase of the output frequency signal, the PLL is operative to reduce the phase error responsive to a periodic indication of the phase error, an occurrence of the request signal is not synchronized in time with the periodic indication of the phase error, a method of operating the radio frequency receiver comprising the steps of:

receiving a radio frequency signal to produce a received signal;

process the received signal to produce the request signal;

operating the radio frequency receiver responsive to the request signal, wherein the step of operating the radio frequency receiver further comprises the step of;

synchronizing the phase of the divided reference frequency signal and the phase of the feedback signal in the PLL, wherein the step of synchronizing further comprises the steps of;

detecting the request signal having first and second states corresponding to first and second states of the PLL;

when the detected requested signal is in the first state, holding each of the divided reference frequency signal and the feedback signal in a predetermined state; and

when the detected requested signal is in the second state;

enabling the divided reference frequency signal responsive to the phase of the reference frequency signal;

determining a phase relationship between reference frequency signal and the output frequency signal; and

enabling the feedback signal responsive to enabling the divided reference frequency signal and the determined phase relationship.

11. A phase locked loop (PLL) having a first and a second state responsive to a request signal, the PLL is operative to reduce a phase error responsive to a periodic indication of the phase error, an occurrence of the request signal is not synchronized in time with the periodic indication of the phase error, the PLL comprising:

a reference divider coupled to receive a reference frequency signal and a synchronized divided reference frequency signal, and operative to produce a divided reference frequency signal;

a phase detector coupled to receive the divided reference frequency signal and a feedback signal and operative to produce a phase error signal indicative of a phase difference between a phase of the reference frequency signal and a phase of an output frequency signal;

a loop filter coupled to receive the phase error signal and operative to produce a filtered signal;

a voltage controlled oscillator coupled to receive the filtered signal and a PLL state control signal, and operative to produce the output frequency signal;

a loop divider coupled to receive the output frequency signal, a synchronized feedback signal, and the PLL state control signal, and operative to produce the feedback signal; and

a phase synchronization circuit comprising;

a PLL state control circuit coupled to receive the request signal, the periodic indication of the phase error, and a first reset signal, and operative to produce a set signal and the PLL state control signal;

a signal detector coupled to receive the request signal, the output frequency signal, the reference frequency signal, and the set signal, and operative to produce second and third reset signals;

a timing control circuit coupled to receive the second and third reset signals, and the set signal, and operative to produce first and second timing signals;

a reset circuit coupled to receive the request signal and the first and second timing signals and operative to produce the first reset signal; and

a logic circuit coupled to receive the first and second timing signals, the divided reference frequency signal, and the feedback signal, and operative to synchronize the divided reference frequency signal and the feedback signal to produce the synchronized divided reference frequency signal and the synchronized feedback signal for coupling to the phase detector.