System and method for packaging data into video processor

• US 5,497,197 A
• Filed: 11/04/1993
• Issued: 03/05/1996
• Est. Priority Date: 11/04/1993
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Davis, Carl W., Sampsell, Jeffrey B., Doherty, Donald B., Marshall, Stephen W., Gove, Robert J., Meyer, Richard C., Egan, Joseph G., Heimbuch, Scott D.
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): Cohen, Cheryl
• Application Number:
  US08/147,801
• Time in Patent Office: 852 Days
• Field of Search: 348/568, 348/388, 348/446, 348/448, 348/384, 348/, 345/84, 345/100, 345/196, 345/201, 345/202, 370/118, 365/230.02, 358/431, 341/67
• US Class Current: 348/388.1
• CPC Class Codes: H04N 19/30 using hierarchical techniques, e.g. scalability H04N19/63 takes precedence
• CPC Class Codes: H04N 19/436 using parallelised computational arrangements
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 2005/7466 Control circuits therefor
• CPC Class Codes: H04N 5/14 Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00
• CPC Class Codes: H04N 5/7458 the modulator being an array of deformable mirrors, e.g. digital micromirror device [DMD]
• CPC Class Codes: H04N 7/0122 the input and the output signals having different aspect ratios
• CPC Class Codes: H04N 9/3147 Multi-projection systems displays in general H04N9/12; video walls G06F3/1446, G09G2300/026

Abstract

A system (30) for packing data into a video processor is provided. System (30) comprises demultiplexer (32), first and second first in-first out buffer memories (34) and (36), and multiplexer (38). Demultiplexer (32) divides a field of video data into first and second parts (42) and (44). First and second parts (42) and (44) are stored in first first in-first out buffer memories (34) and (36), respectively. Multiplexer (38) combines one line from first first in-first out buffer memory (34) with one line from second first in-first out buffer memory (36) to form a single line for processing.

Claims

1. A system for packing data in a video processor, comprising:

a plurality of buffer memories, each operable to store video lines for a horizontal strip of a video field; and

a multiplexer responsive to said buffer memories and operable to combine one line of video data from each buffer memory into a single line of video data for processing by the video processor so as to allow vertical processing of the video lines for each horizontal strip.

2. The system of claim 1, wherein the plurality of buffer memories comprises two buffer memories.

3. The system of claim 1, wherein the plurality of buffer memories comprises first and second first in-first out buffer memories.

4. The system of claim 1, and further comprising a demultiplexer for communicating the horizontal strips of video field to said buffer memories.

5. A system for packing data in a video processor, comprising:

a demultiplexer operable to receive a video signal and operable to create horizontal strips of each video field;

a plurality of buffer memories responsive to said demultiplexer, each operable to store video lines for a horizontal strip of a video field; and

a multiplexer responsive to said buffer memories and operable to combine one line of video data from each buffer memory into a single line of video data for processing by the video processor so as to allow vertical processing of the video lines for each horizontal strip.

6. The system of claim 5, wherein the plurality of buffer memories comprises first and second buffer memories.

7. The system of claim 5, wherein the plurality of buffer memories comprises first and second first in-first out buffer memories.

8. A method for packing video data in a video processor, comprising the steps of:

storing a plurality of horizontal strips of a video field in a plurality of buffer memories;

combining one line of video data stored in each buffer memory to form a single line of video data for processing by the video processor;

communicating the combined line of video data to the video processor; and

performing vertical processing on said combined line of video data at said video processor.

9. The method of claim 8, wherein the step of storing a plurality of horizontal strips comprises the step of storing a first horizontal strip comprising approximately the top half of a video field and storing a second horizontal strip comprising approximately the bottom half of a video field.

10. The method of claim 8, wherein the step of storing a plurality of horizontal strips comprises the step of storing horizontal strips that overlap with adjacent strips for vertical processing.