Power semiconductor device including terminal plates located between two substrates that functions as electrical connectors and mechanical supports

• US 5,497,291 A
• Filed: 06/01/1995
• Issued: 03/05/1996
• Est. Priority Date: 12/26/1991
• Status: Expired due to Term

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Hosen, Toru
• Primary Examiner(s): SPARKS, DONALD ALAN
• Application Number:
  US08/456,925
• Time in Patent Office: 278 Days
• Field of Search: 174/52.1, 174/52.4, 174/138 C, 174/166 S, 257/678, 257/723, 257/724, 257/692, 257/691, 257/690, 257/796, 361/728, 361/735, 361/736, 361/784, 361/785, 361/786, 361/788, 361/787, 361/789, 361/790, 361/791, 361/803, 361/804, 361/807, 361/808, 361/809, 361/810, 361/758, 361/770 , 361/742, 437/925, 439/43, 439/44, 439/45, 439/65, 439/68, 439/69, 439/74, 439/75, 439/76, 439/78, 439/493, 439/507
• US Class Current: 361/804
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 25/162 the devices being mounted on two or more different substrates
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/16195 Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H05K 1/05 Insulated conductive substrates, e.g. insulated metal substrate
• CPC Class Codes: H05K 1/144 Stacked arrangements of planar printed circuit boards

Abstract

A power semiconductor device having power chips mounted on a metal insulating substrate and terminal plates corresponding to inner connection wiring for a main circuit of the device. Electronic parts forming a control circuit are mounted on a second substrate disposed over the first substrate and supported by the terminal plates. Additionally, it is preferable to use a copper plate as wiring material for the main circuit.

Claims

1. A power semiconductor device comprising:

a first substrate having a planar surface;

a plurality of power chips mounted on said planar surface of first substrate;

an output terminal mounted on said first substrate;

a plurality of terminal plates, separate from said first substrate, for connecting said power chips to said output terminal and to each other, each of said plurality of terminal plates being spaced apart from said first substrate and having at least two ends extending toward and connected to said planar surface of said first substrate;

a second substrate supported apart from said first substrate by said plurality of terminal plates;

a control circuit formed on said second substrate;

a terminal connecting said second substrate to said first substrate;

wiring connecting said control circuit to said power chips through said connecting terminal.

2. A power semiconductor device according to claim 1 wherein said first substrate comprises:

a metal plate having a planar surface;

an insulating layer formed on said planar surface of said metal plate; and

a conductive pattern of copper foil formed on said insulating surface.

3. A power semiconductor device according to claim 1, further comprising:

a package covering said plurality of power chips, said control circuit, said second substrate, said connecting terminal, said wiring, and said plurality of terminal plates and said planar surface of said first substrate;

said output terminal being connected to said first substrate extending outward from said planar surface of said first substrate and through said package.

4. A power semiconductor device according to claim 1 wherein at least one of said plurality of terminal plates includes a portion disposed above said first substrate at a height different than a height at which at least one other of said plurality of terminal plates in disposed.

5. A power semiconductor device according to claim 1, wherein at least one of said plurality of terminal plates includes a branch disposed above said substrate, said branch having an end extending parallel to said planar surface of said substrate.