System and method for testing a circuit network having elements testable by different boundary scan standards

• US 5,497,378 A
• Filed: 11/02/1993
• Issued: 03/05/1996
• Est. Priority Date: 11/02/1993
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Van Vliet, Kimberly K., Molina, Andres M., Amini, Ismael Z., Heybruck, William F.
• Primary Examiner(s): Voeltz, Emanuel T.
• Assistant Examiner(s): PEESO, THOMAS R
• Application Number:
  US08/146,557
• Time in Patent Office: 854 Days
• Field of Search: 371/22.3, 371/22.1, 371/22.6, 371/27, 327/202, 364/490, 364/489
• US Class Current: 714/727
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G01R 31/318558 Addressing or selecting of subparts of the device under test
• CPC Class Codes: G11C 29/46 Test trigger logic

Abstract

Disclosed is a test method and system for boundary testing a circuit network. The network, made up of individual integrated circuit chips mounted on a printed circuit card or board, has at least one integrated circuit that is testable by IEEE 1149.1 Standard boundary testing, and at least one second integrated circuit that is testable by Level Sensitive Scan Design boundary testing but not by IEEE 1149.1 Standard boundary testing. The test system has a test access port interface with a test access port controller with Test Clock, Test Data In, Test Data Out, Test Mode Select, and Test Reset I/O. The test access port also has an instruction register, a bypass register, a test clock generator, and a Level Sensitive Scan Device boundary scan register.

Claims

1. A test fixture for boundary testing a circuit network having at least one first integrated circuit testable by IEEE 1149.1 Standard boundary testing, and at least one second integrated circuit testable by Level Sensitive Scan Design boundary testing but not by IEEE 1149.1 Standard boundary testing, and requiring three clocks for testing;

said test fixture comprising a test access port interface comprising;

a. a test access port controller with Test Clock, Test Data In, Test Data Out, Test Mode Select, and Test Reset I/O means;

b. an instruction register;

c. a bypass register;

d. a test clock; and

e. a Level Sensitive Scan Device boundary scan register having the control input signals;

i. LSSD clocks CLK A, CLK B, and CLK C;

ii. boundary scan output BSCO controlling boundary scan cells on the Level Sensitive Scan Device integrated circuit chip associated with drivers;

iii. boundary scan input BSCI controlling boundary scan cells on the Level Sensitive Scan Device integrated circuit chip associated with receivers; and

iv. data inhibit, DI1.

2. The test fixture of claim 1 wherein the Level Sensitive Scan Device Boundary Scan Register controls BSCO and BSCI when Test Access Port control lines Shift Data Register SHIFTDR, and Boundary Scan Register Select BSSEL are high.

3. The test fixture of claim 1 wherein the Level Sensitive Scan Device Boundary Scan Register controls BSCO and BSCI when Test Access Port control lines Update Data Register UPDATDR, and Boundary Scan Register Select BSSEL are high.

4. The test fixture of claim 1 wherein the Data Inhibit Signal DI1 is high and data is sent out to the circuit network from the Level Sensitive Scan Device integrated circuit chip when Boundary Scan Select BSSEL and one of Update Data Register, select Data Register, or Capture Data Register is high.

5. The test fixture of claim 1 wherein the Data Inhibit DI1 is connected to the inhibit pins of the Level Sensitive Scan Device whereby when DI1 is low no signals are transmitted over the circuit network from non-selected second integrated circuit chips.

6. The test fixture of claim 1 wherein the Data Inhibit DI1 is connected to the inhibit pins of the Level Sensitive Scan Device whereby when DI1 is high the Level Sensitive Scan Device chip drivers are enabled and Level Sensitive Scan Device boundary scan cell contents are transmitted over the circuit network from selected second integrated circuit chips.

7. A method for boundary testing a circuit network having at least one first integrated circuit testable by IEEE 1149.1 Standard boundary testing, and at least one second integrated circuit testable by Level Sensitive Scan Design boundary testing but not by IEEE 1149.1 Standard boundary testing, and requiring three clocks for testing;

said method comprising inserting said circuit network in a test fixture comprising a test access port interface comprising;

a. a test access port controller with Test Clock, Test Data In, Test Data Out, Test Mode Select, and Test Reset I/O means;

b. an instruction register;

c. a bypass register;

d. a test clock generator; and

e. a Level Sensitive Scan Device boundary scan register having the control input signals;

i. LSSD clocks CLK A, CLK B, and CLK C;

ii. boundary scan output BSCO controlling boundary scan cells on the Level Sensitive Scan Device integrated circuit chip associated with drivers;

iii. boundary scan input BSCI controlling boundary scan cells on the Level Sensitive Scan Device integrated circuit chip associated with receivers; and

iv. data inhibit, DI1; and

applying test signals to the IEEE 1149.1 Standard first integrated circuit through the test access port controller, and applying test signals to the Level Sensitive Scan Device second integrated circuit through the test access port and the Level Sensitive Scan Device boundary scan register.

8. The method of claim 7 wherein the Level Sensitive Scan Device Boundary Scan Register controls BSCO and BSCI when Test Access Port control lines Shift Data Register SHIFTDR, and Boundary Scan Register Select BSSEL are high.

9. The method of claim 7 wherein the Level Sensitive Scan Device Boundary Scan Register controls BSCO and BSCI when Test Access Port control lines Update Data Register UPDATDR, and Boundary Scan Register Select BSSEL are high.

10. The method of claim 7 wherein the Data Inhibit Signal DI1 is high and data is sent out to the circuit network from the Level Sensitive Scan Device integrated circuit chip when Boundary Scan Select BSSEL and one of Update Data Register, Select Data Register, or Capture Data Register is high.

11. The method of claim 7 herein the Data Inhibit DI1 is connected to the inhibit pins of the Level Sensitive Scan Device whereby when DI1 is low no signals are transmitted over the circuit network from non-selected second integrated circuit chips.

12. The method of claim 7 wherein the Data Inhibit DI1 is connected to the inhibit pins of the Level Sensitive Scan Device whereby when DI1 is high the Level Sensitive Scan Device chip drivers ate enabled and Level Sensitive Scan Device boundary scan cell contents are transmitted over the circuit network from selected second integrated circuit chips.