Bitstream defect analysis method for integrated circuits

• US 5,497,381 A
• Filed: 06/01/1995
• Issued: 03/05/1996
• Est. Priority Date: 10/15/1993
• Status: Expired due to Term

• Current Assignee: MediaTek, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: O'Donoghue, Geoffrey P., Cheek, Gary C.
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US08/458,020
• Time in Patent Office: 278 Days
• Field of Search: 371/29.1
• US Class Current: 714/745
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2223/5446 Located in scribe lines
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Defects in the manufacturing of IC devices are analyzed by testing the devices for defects, generating a serial digital data bitstream upon which the test result for each device is encoded in succession, and operating upon the data bitstream to analyze the device defects. This allows for the use of rapid and reliable digital signal processing techniques to perform the analysis. The types of analyses that can be performed include the determination of non-random yields to distinguish random from systematic defects, comparisons with signature defect patterns that correspond to various systematic faults, and yield predictions for other circuits manufactured with a similar process but having a different critical circuit area. An improved windowing technique is used to determine non-random defects, in which normalized defect counts are obtained and compared for various window sizes. Multiple functional and parametric tests for each device can be accommodated in several ways, including the assignment of additional data bits in the bitstream to the additional tests. The defect analysis can be performed in real-time on one batch while the next batch is being processed, with the results of the analysis used to correct the manufacturing process if systematic defects are identified. An improved method is also described for calculating the non-random yield loss factor Y_o, which can be used in yield models for yield prediction purposes.

Claims

1. A method of controlling the fabrication of multiple integrated circuit (IC) dice fabricated on respective IC wafers, with each wafer having multiple dice, comprising:

fabricating an IC wafer having multiple IC dice located at predetermined positions on the wafer,

testing the IC dice on said IC wafer for defects in a sequence that corresponds to the positions of said dice on the wafer,

encoding the results of said testing into an output signal in the form of a serial digital data bitstream with a bit sequence that corresponds to the test sequence and the positions of said dice on said wafer,

operating upon the dice positional information in said data bitstream output signal to categorize defects identified in said dice by said testing, and

modifying the fabrication for subsequent wafers based upon the results of said defect categorization.

2. The method of claim 1, wherein multiple respective data bits of said data bitstream are assigned to each of said dice.

3. The method of claim 2, wherein multiple tests are performed on each of said dice, and the results of different tests are encoded onto different data bits for each of said dice.

4. The method of claim 3, wherein said data bitstream is processed to distinguish between random and systematic defects in said dice.

5. The method of claim 4, wherein said data bitstream is processed by a windowing analysis to determine the non-random yield (Y_o) of said dice.

6. The method of claim 5, wherein said data bitstream is generated by assigning one bit state to data bits that correspond to defective dice, and a different bit state to data bits that correspond to non-defective dice, and said data bitstream is analyzed by:

determining the number defective bit states in the bitstream,

applying at least one multi-bit window to said bitstream to determine a respective defect count for such window, said defect counts being equal to the number of window positions that include at least one defective bit state for their respective window sizes,

normalizing said defect counts by the number of bits included within their respective windows, and

comparing the normalized defect count for at least one multi-bit window with the number of defective bit states in the bitstream to obtain an indication of the systematic defect rate in said dice.

7. The method of claim 6, wherein a four-bit window is applied to said bitstream, a normalized defect count is obtained for said four-bit window, and an indication of the systematic defect rate in said IC dice is obtained by comparing the normalized defect count of said four-bit window with the number of defective bit states in said bitstream.

8. The method of claim 7, wherein two-bit, three-bit and four-bit windows are applied to said bitstream, normalized defect counts are obtained for said two-, three- and four-bit windows, and an indication of the systematic defect rate in said IC dice is obtained by comparing the average of the normalized defect counts for said two-, three- and four-bit windows with the number of defective bit states in said bitstream.

9. The method of claim 4, wherein said dice have predetermined critical circuit areas, said wafer is manufactured by a predetermined manufacturing process, and said data bitstream is processed to predict the yield of dice on other wafers that are manufactured by a similar process but have different critical dice circuit areas, based upon the systematic defects determined for the dice under test.

10. The method of claim 1, wherein said data bitstream is processed to analyze the spatial defect pattern of said dice on said wafer.

11. The method of claim 10, wherein said spatial defect pattern analysis comprises providing signature patterns of respective systematic defects in digital data bitstream formats that correspond to the format of said test digital data bitstream, and correlating said test digital data bitstream with said signature patterns.

12. The method of claim 1, wherein said multiple wafers are manufactured in succession, and the data bitstream for one wafer is processed during manufacture of the next successive wafer.

13. The method of claim 12, wherein the data bitstreams for said wafers are processed to distinguish between random and systematic defects, and the results for one of said wafers is used to modify the manufacturing process for subsequent wafers in response to detected systematic defects.

14. The method of claim 1, wherein said testing is performed by a test device that generates a test output, and said digital data bitstream is generated from said test output without manual intervention.