Method and apparatus for providing a high through put cache tag controller

• US 5,497,470 A
• Filed: 05/18/1992
• Issued: 03/05/1996
• Est. Priority Date: 05/18/1992
• Status: Expired due to Fees

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Liencres, Bjorn
• Primary Examiner(s): Powell, Mark R.
• Application Number:
  US07/885,118
• Time in Patent Office: 1,387 Days
• Field of Search: 395/425, 395/403, 395/467, 395/468
• US Class Current: 711/3
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence

Abstract

A cache tag controller for a cache tag memory for receiving multiple consecutive cache tag modify operations through a system bus to update cache tags in the cache tag memory. The cache tag controller comprises memory for storing cache tags; address register coupled to the memory for specifying a cache tag in the memory, the address register receiving a first modify operation from a system bus; read register coupled to the memory for reading the cache tag according to the address; first update circuit coupled to the read register for modifying the cache tag based on the first modify operation; stage register coupled to the first update circuit for storing an updated cache tag outputted from the first update circuit in response to the first modify operation; compare circuit coupled to the system bus for determining whether a second modify operation from the system bus is for the same cache tag in the memory as the first modify operation, the second modify operation being transmitted from said system bus before the first modify operation completes writing to the memory; second update circuit coupled to the stage register and compare circuit for modifying the updated cache tag in the stage register means according to the second modify operation if the modify operation is for the same cache tag as the first modify operation; and write register coupled to the memory for writing the first and second updated cache tags to the memory means as specified by the address from the address register.

Claims

1. A cache tag controller for a cache tag memory coupled to a system bus for receiving multiple cache tag modify operations to update cache tags in said cache tag memory said cache tag controller comprising:

memory means for storing cache tags;

address register means coupled to said memory means for specifying a cache tag in said memory means, said address register means receiving a first modify operation from said system bus;

read register means coupled to said memory means for reading said cache tag according to said address means;

first update means coupled to said read register means for modifying said cache tag based on said first modify operation;

stage register means coupled to said first update means for storing a once-updated cache tag outputted from said first update means in response to said first modify operation;

compare means coupled to said system bus for determining whether a second modify operation, the second modify operation being received subsequent to the first modify operation being received by the address register means from said system bus, is for the same cache tag in said memory means as said first modify operation, if said second modify operation is transmitted from said system bus before said first modify operation completes writing to said memory means;

second update means coupled to said stage register means and said compare means for modifying said once-updated cache tag in said stage register means according to said second modify operation if said modify operation is for the same cache tag as said first modify operation; and

write register means coupled to said memory means for writing at least one of the once-updated cache tag and a twice-updated cache tag to said memory means as specified by said address from said address register means.

2. A cache tag controller according to claim 1, further comprising:

first pipeline means coupled between said address register means and said stage register means for delaying said second modify operation until said first modify operation completes its operation by storing said first updated cache tag in said stage register means;

second pipeline means coupled to said stage register means for delaying said second updated cache tag until said first updated cache tag is written to said memory means.

3. A cache tag controller according to claim 2, wherein said first pipeline means is a register and said second pipeline means is a feedback into said stage register means.

4. A cache tag controller according to claim 1, wherein said memory means is a single-port RAM.

5. A cache tag controller according to claim 1, wherein said modify operation specifies a tag address in said cache tag memory and updates at least one flag in the cache tag.

6. A cache tag controller according to claim 5, wherein said modify operation writes directly to a cache tag stored in the memory means, and changes at least one of an address field and an index field in the cache tag.

7. A method of updating a cache tag memory having a plurality of cache tags, the cache memory being coupled to a system bus for receiving multiple cache tag modify operations to update cache tags in said cache tag memory, said method comprising the steps of:

receiving a first modify operation from said system bus by address register means coupled to said memory means, said first modify operation specifying a cache tag in said memory means;

reading said cache tag according to said address means by read register means coupled to said memory means;

modifying said cache tag based on said first modify operation by first update means coupled to said read register means;

storing a once-updated cache tag outputted from said first update means in response to said first modify operation in stage register means coupled to said first update means;

receiving a second modify operation from said system bus;

determining whether said second modify operation, the second modify operation being received subsequent to the first modify operation being received by the address register means from said system bus, is for the same cache tag in said memory means as said first modify operation by compare means coupled to said system bus, if said second modify operation is transmitted from said system bus before said first modify operation completes writing to said memory means;

modifying said once-updated cache tag in said stage register means according to said second modify operation by second update means coupled to said stage register means and said compare means, if said modify operation is for the same cache tag as said first modify operation; and

writing at least one of the once-updated cache tag and a twice-updated cache tag to said memory means as specified by said address from said address register means by write register means coupled to said memory means.

8. A method according to claim 7, further comprising the steps of:

delaying said second modify operation until said first modify operation completes its operation by storing said first updated cache tag in said stage register means by first pipeline means coupled between said address register means and said stage register means; and

delaying said second updated cache tag until said first updated cache tag is written to said memory means by second pipeline means coupled to said stage register means.

9. A method according to claim 8, wherein said first pipeline means is a register and said second pipeline means is a feedback into said stage register means.

10. A method according to claim 7, wherein said memory means is a single-port RAM.

11. A method according to claim 7, wherein said modify operation specifies a tag address in said cache tag memory and updates at least one flag in the cache tag.

12. A method according to claim 11, wherein each of said modify operation writes directly to a cache tag stored in memory means, and changes at least one of an address field and an index field in the cache tag.