Process for forming an electrically programmable read-only memory cell

• US 5,498,560 A
• Filed: 09/16/1994
• Issued: 03/12/1996
• Est. Priority Date: 09/16/1994
• Status: Expired due to Fees

• Current Assignee: Motorola Solutions, Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Woo, Michael P., Sharma, Umesh
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/311,162
• Time in Patent Office: 543 Days
• Field of Search: 437/43, 437/44, 437/50, 437/195, 437/191
• US Class Current: 438/261
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

EPROM cells include T-shaped floating gates (61, 171) and control gates that surround virtually all of the floating gates (61, 171) except for the portion of the floating gates (61, 171) that lie on a gate dielectric layer (51, 151). The EPROM cells may include customized well regions (22, 122) to allow flash erasing or individual cell erasing for electrically erasable EPROMs. Many different configurations of the memory cells are possible. The configurations of the source regions, drain regions, and well regions (22, 122) may be determined by how a user of the memory cells wants to program or erase the memory cells.

Claims

1. A process for forming an electrically programmable read-only memory cell comprising the steps of:

forming a first layer over a semiconductor substrate;

forming an opening through the first layer;

forming a spacer adjacent to the opening in the first layer;

forming a floating gate overlying the substrate, wherein the floating gate has a T-shape and is formed after the step of forming the spacer;

removing the first layer and spacer after the step of forming the floating gate;

forming an intergate dielectric layer lying adjacent to the floating gate, wherein the intergate dielectric layer has a uniform thickness adjacent to the floating gate; and

forming a control gate lying adjacent to the intergate dielectric layer, wherein a portion of the control gate underlies a portion of the floating gate.

2. The process of claim 1, wherein the step of forming the intergate dielectric layer is performed such that the intergate dielectric layer includes oxide-nitride-oxide and has an electrically measured oxide equivalent thickness in a range of 50-300 angstroms.

3. The process of claim 1, further comprising steps of:

forming a tunnel dielectric layer having a thickness in a range of 50-150 angstroms before the step of forming the floating gate; and

forming a first doped region and a second doped region, wherein;

the first and second doped regions lie within the substrate and define a channel region; and

at least a portion of the channel region underlies the floating gate.

4. The process of claim 1, wherein the control gate is also a select gate for the memory cell.

10. The process of claim 1 further comprising a step of forming a gate dielectric layer underlying the opening after the step of forming the spacer, wherein the step of forming the floating gate comprises steps of:

forming a silicon layer within the opening, adjacent to the spacer, and over the first layer; and

patterning the silicon layer to form the floating gate.

5. A process for forming a semiconductor device including a first plurality of electrically programmable read-only memory cells comprising the steps of:

forming a first well region having a first conductivity type within a semiconductor substrate having a second conductivity type that is opposite the first conductivity type;

forming a second well region having the second conductivity type within the first well region;

forming floating gates, wherein;

a first plurality of floating gates are formed over the substrate;

a second plurality of floating gates are formed over the first well region; and

a third plurality of floating gates are formed over the second well region;

forming an intergate dielectric layer lying adjacent the floating gates; and

forming word lines lying adjacent to the intergate dielectric layer.

6. The process of claim 5, wherein:

the step of forming the second well region is performed such that at least one other second well region is formed, wherein;

the at least one other second well region has the second conductivity type;

the at least one other second well region lies within the first well region; and

the second well regions are spaced apart from each other; and

the step of forming the floating gates is performed such that a fourth plurality of floating gates are formed over the at least one other second well region.

7. The process of claim 6, wherein the step of forming the floating gates is performed such that the second plurality is equal to the sum of the third and fourth pluralities.

8. The process of claim 5, wherein:

the step of forming the floating gates is performed such that each of the floating gates has a T-shape that includes a trunk portion and a cross-bar portion;

the step of forming the intergate dielectric layer is performed such that the intergate dielectric layer has a uniform thickness along surfaces of the trunk and cross-bar portions of the floating gates; and

the step of forming the word lines is performed such that the word lines lie adjacent to the intergate dielectric layer, wherein portions of the word lines underlie portions of the floating gates.

9. The process of claim 5, wherein the step of forming the intergate dielectric layer is performed such that the intergate dielectric layer includes oxide-nitride-oxide and has an electrically measured oxide equivalent thickness in a range of 50-300 angstroms.

11. A process for forming an electrically programmable read-only memory cell comprising the steps of:

forming a gate dielectric layer over a semiconductor substrate;

forming a floating gate over the gate dielectric layer, wherein the step of forming the floating gate comprises steps of;

forming a first silicon layer over the gate dielectric layer;

patterning the first silicon layer to form a first silicon member;

forming spacers adjacent to the first silicon member;

forming a first layer over the substrate, wherein the spacers and the first layer include different materials;

polishing the first silicon member to form a trunk portion of the floating gate, wherein the trunk portion has a trunk width;

forming a second silicon member over the trunk portion to form the floating gate, wherein;

the second silicon member is a cross-bar portion of the floating gate; and

the cross-bar portion has a cross-bar width that is wider than the trunk width;

forming an intergate dielectric layer lying adjacent to the floating gate, wherein the intergate dielectric layer has a uniform thickness adjacent to the floating gate; and

forming a control gate lying adjacent to the intergate dielectric layer, wherein a portion of the control gate underlies a portion of the floating gate.

12. The process of claim 11, wherein:

the step of forming the gate dielectric layer forms a tunnel dielectric layer having a thickness in a range of 50-150 angstroms; and

the step of forming the intergate dielectric layer is performed such that the intergate dielectric layer includes oxide-nitride-oxide and has an electrically measured oxide equivalent thickness in a range of 50-300 angstroms.

13. The process of claim 11, wherein:

the process further comprises a step of forming a first doped region and a second doped region, wherein;

the first and second doped regions lie within the substrate and define a channel region; and

at least a portion of the channel region underlies the floating gate; and

the control gate is also a select gate for the memory cell.

14. The process of claim 11, wherein the process further comprising steps of:

forming a first layer over the substrate;

forming an opening through the first layer before forming the gate dielectric layer; and

removing the first layer and spacer after the step of forming the floating gate.

15. A process for forming an electrically programmable read-only memory cell comprising the steps of:

forming a gate dielectric layer over a semiconductor substrate;

forming a floating gate on the gate dielectric layer, wherein the floating gate has a T-shape with a wide portion and a narrow portion that lies on the gate dielectric layer;

forming an intergate dielectric layer lying adjacent to the floating gate, wherein the intergate dielectric layer has a uniform thickness adjacent to the floating gate; and

forming a control gate lying adjacent to the intergate dielectric layer, wherein a portion of the control gate underlies a portion of the floating gate.

16. The process of claim 15, wherein the step of forming the intergate dielectric layer is performed such that the intergate dielectric layer includes oxide-nitride-oxide and has an electrically measured oxide equivalent thickness in a range of 50-300 angstroms.

17. The process of claim 15, wherein the step of forming the gate dielectric layer forms a tunnel dielectric layer having a thickness in a range of 50-150 angstroms.

18. The process of claim 15, further comprising a step of forming a first doped region and a second doped region, wherein:

the first and second doped regions lie within the substrate and define a channel region; and

at least a portion of the channel region underlies the floating gate.

19. The process of claim 15, wherein the step of forming the floating gate comprises steps of:

forming a first silicon layer on the gate dielectric layer;

patterning the first silicon layer to form a first silicon member;

forming spacers adjacent to the first silicon member;

forming a first layer over the substrate, wherein the spacers and the first layer include different materials;

polishing the first silicon member to form a trunk portion of the floating gate, wherein the trunk portion has a trunk width; and

forming a second silicon member over the trunk portion to form the floating gate, wherein;

the second silicon member is a cross-bar portion of the floating gate; and

the cross-bar portion has a cross-bar width that is wider than the trunk width.

20. The process of claim 15, wherein the control gate is also a select gate for the memory cell.

21. The process of claim 15, further comprising steps of:

forming a first layer over the substrate;

forming an opening through the first layer;

forming a spacer adjacent to the opening in the first layer before the step of forming the floating gate; and

removing the first layer and spacer after the step of forming the floating gate.

22. The process of claim 21, wherein:

the step of forming the gate dielectric layer is performed after the step of forming the spacer; and

the step of forming the floating gate comprises steps of;

forming a silicon layer within the opening, adjacent to the spacer, and over the first layer; and

patterning the silicon layer to form the floating gate.