Method of fabricating memory cell for semiconductor integrated circuit

• US 5,498,561 A
• Filed: 07/15/1992
• Issued: 03/12/1996
• Est. Priority Date: 11/30/1990
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Sakuma, Toshiyuki, Miyasaka, Yoichi
• Primary Examiner(s): Forson, George
• Assistant Examiner(s): Booth, Richard A.
• Application Number:
  US07/914,023
• Time in Patent Office: 1,336 Days
• Field of Search: 437/47, 437/48, 437/52, 437/228, 437/60, 437/919, 437/977, 216/6, 216/22
• US Class Current: 438/396
• CPC Class Codes: H10B 12/01 Manufacture or treatment

Abstract

According to a method of fabricating a memory cell for a semiconductor integrated circuit, a lower electrode having a predetermined shape is formed on a semiconductor layer. A first insulating interlayer is formed on an entire surface of the semiconductor layer such that only a top surface of the lower electrode is exposed. A dielectric having a high dielectric constant is formed on the lower electrode and on the semiconductor layer. An upper electrode is formed on the dielectric having a high dielectric constant. The upper electrode constitutes a capacitor with the lower electrode through the dielectric.

Claims

1. A method of fabricating a capacitor of a memory cell, including an MOS transistor and the capacitor, for a semiconductor integrated circuit, comprising the steps of:

forming a lower electrode on an insulating layer;

forming a first insulating interlayer on the entire surface of said insulating layer and said lower electrode;

forming a photoresist on the entire surface of said first insulating interlayer;

etching said photoresist and said first insulating interlayer such that only the top surface of said lower electrode is exposed;

forming a strontium titanium dielectric on said lower electrode and on said first insulating interlayer; and

forming an upper electrode on said dielectric, said upper electrode constituting the capacitor with said lower electrode through said dielectric.

2. A method according to claim 1, wherein said lower electrode consists of polysilicon on top of which a barrier metal is stacked, and said first insulating interlayer has an upper surface which is even with that of said barrier metal.

3. A method according to claim 1, wherein the MOS transistor has diffusion regions corresponding to a source and a drain, has a gate arranged between said diffusion regions via an insulation film, and is formed on a semiconductor substrate.

4. A method according to claim 3, wherein said insulating layer is formed on said semiconductor substrate to cover said gate, and said lower electrode is formed on said insulating layer and connected to said diffusion regions of said semiconductor substrate.

5. A method according to claim 3, wherein a bit line of said memory cell is formed on a surface of said semiconductor substrate so as to be in contact with said diffusion layers, and said gate constitutes a word line.

6. A method of fabricating a capacitor of a memory cell, including an MOS transistor and the capacitor, for a semiconductor integrated circuit, comprising the steps of:

forming a lower electrode on an insulating layer;

forming a first insulating interlayer on only side surfaces of said lower electrode as sidewall spaces;

forming a strontium titanate dielectric on said lower electrode and said insulating layer; and

forming an upper electrode on said dielectric, said upper electrode constituting the capacitor with said lower electrode through said dielectric.

7. A method according to claim 6, wherein the MOS transistor has diffusion regions corresponding to a source and a drain, has a gate arranged between said diffusion regions via an insulating film, and is formed on a semiconductor substrate.

8. A method according to claim 7, wherein said insulating layer is formed on said semiconductor substrate to cover said gate, and said lower electrode is formed on said insulating layer and connected to said diffusion regions on said semiconductor substrate.

9. A method according to claim 7, wherein a bit line of said memory cell is formed on a surface of said semiconductor substrate so as to be in contact with said diffusion regions, and said gate constitutes a word line.

10. A method of fabricating a capacitor of a memory cell, including an MOS transistor and the capacitor, for a semiconductor integrated circuit, comprising the steps of:

forming a lower electrode on an insulating layer;

forming a strontium titanate dielectric film on said lower electrode, and etching said film back to a thickness by wet etching; and

forming an upper electrode directly on said dielectric film without any intervening insulating layer, said upper electrode constituting the capacitor with said lower electrode through said dielectric.

11. A method according to claim 10, wherein the MOS transistor has diffusion regions corresponding to a source and a drain, has a gate arranged between said diffusion regions via an insulating film, and is formed on a semiconductor substrate.

12. A method according to claim 11, wherein said insulating layer is formed on said semiconductor substrate to cover said gate, and said lower electrode is formed on said insulating layer and connected to said diffusion regions on said semiconductor substrate.

13. A method according to claim 11, wherein a bit line of said memory cell is formed on a surface of said semiconductor substrate so as to be in contact with said diffusion regions, and said gate constitutes a word line.