Method of fabricating memory cell for semiconductor integrated circuit
First Claim
1. A method of fabricating a capacitor of a memory cell, including an MOS transistor and the capacitor, for a semiconductor integrated circuit, comprising the steps of:
- forming a lower electrode on an insulating layer;
forming a first insulating interlayer on the entire surface of said insulating layer and said lower electrode;
forming a photoresist on the entire surface of said first insulating interlayer;
etching said photoresist and said first insulating interlayer such that only the top surface of said lower electrode is exposed;
forming a strontium titanium dielectric on said lower electrode and on said first insulating interlayer; and
forming an upper electrode on said dielectric, said upper electrode constituting the capacitor with said lower electrode through said dielectric.
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Abstract
According to a method of fabricating a memory cell for a semiconductor integrated circuit, a lower electrode having a predetermined shape is formed on a semiconductor layer. A first insulating interlayer is formed on an entire surface of the semiconductor layer such that only a top surface of the lower electrode is exposed. A dielectric having a high dielectric constant is formed on the lower electrode and on the semiconductor layer. An upper electrode is formed on the dielectric having a high dielectric constant. The upper electrode constitutes a capacitor with the lower electrode through the dielectric.
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Citations
13 Claims
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1. A method of fabricating a capacitor of a memory cell, including an MOS transistor and the capacitor, for a semiconductor integrated circuit, comprising the steps of:
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forming a lower electrode on an insulating layer; forming a first insulating interlayer on the entire surface of said insulating layer and said lower electrode; forming a photoresist on the entire surface of said first insulating interlayer; etching said photoresist and said first insulating interlayer such that only the top surface of said lower electrode is exposed; forming a strontium titanium dielectric on said lower electrode and on said first insulating interlayer; and forming an upper electrode on said dielectric, said upper electrode constituting the capacitor with said lower electrode through said dielectric. - View Dependent Claims (2, 3, 4, 5)
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6. A method of fabricating a capacitor of a memory cell, including an MOS transistor and the capacitor, for a semiconductor integrated circuit, comprising the steps of:
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forming a lower electrode on an insulating layer; forming a first insulating interlayer on only side surfaces of said lower electrode as sidewall spaces; forming a strontium titanate dielectric on said lower electrode and said insulating layer; and forming an upper electrode on said dielectric, said upper electrode constituting the capacitor with said lower electrode through said dielectric. - View Dependent Claims (7, 8, 9)
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10. A method of fabricating a capacitor of a memory cell, including an MOS transistor and the capacitor, for a semiconductor integrated circuit, comprising the steps of:
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forming a lower electrode on an insulating layer; forming a strontium titanate dielectric film on said lower electrode, and etching said film back to a thickness by wet etching; and forming an upper electrode directly on said dielectric film without any intervening insulating layer, said upper electrode constituting the capacitor with said lower electrode through said dielectric. - View Dependent Claims (11, 12, 13)
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Specification