Semiconductor processing methods of forming stacked capacitors

• US 5,498,562 A
• Filed: 04/29/1994
• Issued: 03/12/1996
• Est. Priority Date: 04/07/1993
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Walker, Michael A., Dennison, Charles H.
• Primary Examiner(s): Thomas, Tom
• Application Number:
  US08/237,371
• Time in Patent Office: 683 Days
• Field of Search: 437/47, 437/48, 437/52, 437/60, 437/919, 437/238, 257/306
• US Class Current: 438/253
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor

Abstract

In one aspect of the invention, an insulative nitride oxidation barrier layer is provided over a cell polysilicon layer to a thickness of at least about 150 Angstroms. An insulating layer is provided above the nitride oxidation barrier layer, and an contact/container is etched therethrough and through dielectric and cell polysilicon layers. Such exposes edges of the cell polysilicon within the contact/container. The wafer is then exposed to an oxidizing ambient to oxidize the cell polysilicon exposed edges, with the nitride oxidation barrier layer during such oxidation exposure inhibiting oxidation of the outer surface of the cell polysilicon layer. In another aspect, a multi-container stacked capacitor construction has its containers defined or otherwise electrically isolated in a single CMP step. In another aspect, a combination etch stop/oxidation barrier layer or region is provided to enable exposure of a precise quantity of the outside walls of a stacked capacitor container.

Claims

1. A semiconductor processing method of forming a memory cell having a stacked container capacitor on a semiconductor wafer, the method comprising the following steps:

providing a word line and a pair of adjacent source/drain areas, the word line having sidewalls and a top, the sidewalls and top being covered by a first insulating material;

providing a planarized underlying layer of insulating material atop the wafer over the word line and source/drain areas, the planarized underlying layer having a planar upper surface which is elevationally above the first insulating material;

providing a combination etch stop and oxidation barrier insulative layer over the planar upper surface of the underlying insulating layer, the combination layer being different in composition from the insulating material of the underlying layer;

providing an intermediate layer of insulating material over the combination layer, the insulating material of the intermediate layer being different in composition from the insulating material of the combination layer with the insulating material of the intermediate layer being selectively etchable relative to the insulating material of the combination layer;

etching a capacitor contact/container opening through the intermediate, combination and underlying insulating layers to one of the source/drain areas, the capacitor contact/container opening having a first open width;

providing a first layer of conductive material above the intermediate layer and within the first contact/container opening over the one source/drain area, the first layer of conductive material being provided to a thickness which is less than one half the first open width leaving a second outward opening having a second open width which is less than the first open width, the first layer of conductive material being selected such that the intermediate and underlying insulating layers are selectively etchable relative to the first layer of conductive material;

removing the first layer conductive material from above the intermediate insulating layer to define an isolated capacitor storage node container, the isolated capacitor storage node having sidewalls having inner surfaces and outer surfaces;

etching the intermediate insulating layer selectively relative to the isolated capacitor storage node and combination layer, and using the combination layer as an etch stop during such etching to expose only a portion of the outer surfaces of the isolated capacitor storage node sidewalls;

providing a capacitor dielectric layer over exposed inner and outer sidewall surfaces of the isolated capacitor storage node;

providing a cell polysilicon layer over the capacitor dielectric layer, the cell polysilicon layer having an outer surface;

providing an electrically insulative nitride oxidation barrier layer over the cell polysilicon layer to a thickness of at least about 150 Angstroms;

providing an overlying layer of insulating material above the nitride oxidation barrier layer, the insulating material of the overlying layer comprising the insulating material of the underlying layer;

providing a masking layer above the overlying layer, the masking layer being selected such that material of the overlying and underlying layers is selectively etchable relative to the masking layer;

etching a bit line contact/container opening over the other source/drain area through the masking, overlying, nitride oxidation barrier and cell polysilicon layers, and using the combination layer as an etch stop during such bit line contact/container opening etching, the bit line contact/container opening having sidewalls, the bit line contact/container opening sidewalls including an exposed edge of the cell polysilicon layer;

exposing the wafer having the bit line contact/container opening to an oxidizing ambient to oxidize the cell polysilicon exposed edge, the nitride oxidation barrier layer during such oxidation exposure inhibiting oxidation of the outer surface of the cell polysilicon layer, the combination layer during such oxidation exposure inhibiting oxidation of the isolated capacitor storage node;

etching the combination layer from within the bit line contact/container opening;

etching the underlying layer from within the bit line contact/container opening to outwardly expose the other source/drain area; and

depositing a conductive material atop the wafer and within the bit line contact/container opening over the exposed other source/drain area, and patterning such conductive material to form a bit line.

2. A semiconductor processing method of forming a memory cell of claim 1 wherein the first insulating material comprises nitride, and the underlying layer of insulating material comprises oxide.

3. A semiconductor processing method of forming a memory cell of claim 1 wherein the combination layer is provided to a thickness of from about 100 Angstroms to about 4000 Angstroms.

4. A semiconductor processing method of forming a memory cell of claim 1 wherein the combination layer comprises nitride.

5. A semiconductor processing method of forming a memory cell of claim 1 wherein the combination layer comprises SiO₂ deposited by decomposition of tetraethylorthosilicate (TEOS), the underlying layer comprising SiO₂ of another form.

6. A semiconductor processing method of forming a memory cell of claim 1 wherein the first layer of conductive material comprises polysilicon.

7. A semiconductor processing method of forming a memory cell of claim 1 wherein the first layer of conductive material comprises polysilicon, and the intermediate and underlying layers comprise oxide.

8. A semiconductor processing method of forming a memory cell of claim 1 wherein the overlying and underlying layers comprise oxide, and the combination layer comprises nitride.

9. A semiconductor processing method of forming a memory cell of claim 1 wherein the masking layer comprises nitride.

10. A semiconductor processing method of forming a memory cell of claim 1 wherein the nitride oxidation barrier layer thickness is from about 250 Angstroms to about 1500 Angstroms.

11. A semiconductor processing method of forming a memory cell of claim 1 wherein the step of etching the bit line contact/container opening comprises undercut etching cell polysilicon.

12. A semiconductor processing method of forming a memory cell of claim 1 wherein the masking layer and combination layer comprise nitride, the nitride masking layer being provided to a thickness which is greater than that of the nitride combination layer.

13. A semiconductor processing method of forming a memory cell of claim 1 wherein the removing step comprises:

providing sacrificial spacers within the second outward opening inwardly adjacent first layer conductive material inner sidewalls, the sacrificial spacers having a combined width which is less than the second open width leaving a third outward opening having a third open width which is less than the second open width;

providing a second layer of conductive material above the first layer of conductive material and within the third outward opening and over the sacrificial spacers, the second layer of conductive material electrically connecting with the first layer of conductive material within the third outward opening;

chemical-mechanical polishing the second and first conductive layers to the intermediate insulating layer upper surface in a single step to define an isolated capacitor storage node container having sidewalls electrically interconnected with an inner upwardly projecting conductive mass; and

after chemical-mechanical polishing, etching the sacrificial spacers away from the wafer to provide lateral space between the upwardly projecting conductive mass and sidewalls.

14. A semiconductor processing method of forming a memory cell of claim 13 wherein the second layer of conductive material is provided within the third outward opening to a thickness which is less than one half the third open width leaving a fourth outward opening having a fourth width which is less than the third width, the step of chemical-mechanical polishing defining the inner upwardly projecting conductive mass into the shape of a ring.

15. A semiconductor processing method of forming a memory cell having a stacked container capacitor on a semiconductor wafer, the method comprising the following steps:

providing a word line and a pair of adjacent source/drain areas, the word line having sidewalls and a top, the sidewalls and top being covered by a nitride insulating material;

providing a planarized underlying layer of insulating oxide atop the wafer over the word line and source/drain areas, the planarized underlying layer having a planar upper surface which is elevationally above the nitride insulating material;

providing a combination etch stop and oxidation barrier insulative layer of nitride over the planar upper surface of the underlying insulating layer;

providing an intermediate layer of insulating oxide over the combination layer;

etching a capacitor contact/container opening through the intermediate, combination and underlying insulating layers to one of the source/drain areas, the capacitor contact/container opening having a first open width;

providing a first layer of polysilicon above the intermediate layer and within the first contact/container opening over the one source/drain area, the first layer of polysilicon being provided to a thickness which is less than one half the first open width leaving a second outward opening having a second open width which is less than the first open width;

removing the first layer of polysilicon from above the intermediate insulating layer to define an isolated capacitor storage node container, the isolated capacitor storage node having sidewalls having inner surfaces and outer surfaces;

etching the intermediate insulating layer selectively relative to the isolated capacitor storage node and combination layer, and using the combination layer as an etch stop during such etching to expose only a portion of the outer surfaces of the isolated capacitor storage node sidewalls;

providing a capacitor dielectric layer over exposed inner and outer sidewall surfaces of the isolated capacitor storage node;

providing a cell polysilicon layer over the capacitor dielectric layer, the cell polysilicon layer having an outer surface;

providing an electrically insulative nitride oxidation barrier layer over the cell polysilicon layer to a thickness of at least about 150 Angstroms;

providing an overlying layer of insulating oxide above the nitride oxidation barrier layer;

providing a nitride masking layer above the overlying layer, the nitride masking layer being provided to a thickness which is greater than that of the nitride combination layer;

etching a bit line contact/container opening over the other source/drain area through the masking, overlying, nitride oxidation barrier and cell polysilicon layers, and using the nitride combination layer as an etch stop during such bit line contact/container opening etching, the bit line contact/container opening having sidewalls, the bit line contact/container opening sidewalls including an exposed edge of the cell polysilicon layer;

exposing the wafer having the bit line contact/container opening to an oxidizing ambient to oxidize the cell polysilicon exposed edge, the nitride oxidation barrier layer during such oxidation exposure inhibiting oxidation of the outer surface of the cell polysilicon layer, the nitride combination layer during such oxidation exposure inhibiting oxidation of the isolated capacitor storage node;

etching the nitride combination layer from within the bit line contact/container opening;

etching the underlying layer from within the bit line contact/container opening to outwardly expose the other source/drain area; and

depositing a conductive material atop the wafer and within the bit line contact/container opening over the exposed other source/drain area, and patterning such conductive material to form a bit line.

16. A semiconductor processing method of forming a memory cell of claim 15 wherein the removing step comprises:

providing sacrificial spacers within the second outward opening inwardly adjacent first polysilicon layer inner sidewalls, the sacrificial spacers having a combined width which is less than the second open width leaving a third outward opening having a third open width which is less than the second open width;

providing a second layer of polysilicon above the first layer of polysilicon and within the third outward opening and over the sacrificial spacers, the second layer of polysilicon electrically connecting with the first layer of polysilicon within the third outward opening;

chemical-mechanical polishing the second and first polysilicon layers to the intermediate insulating layer upper surface in a single step to define an isolated capacitor storage node container having sidewalls electrically interconnected with an inner upwardly projecting conductive mass; and

after chemical-mechanical polishing, etching the sacrificial spacers away from the wafer to provide lateral space between the upwardly projecting conductive mass and sidewalls.

17. A semiconductor processing method of forming a memory cell of claim 16 wherein the second layer of polysilicon is provided within the third outward opening to a thickness which is less than one half the third open width leaving a fourth outward opening having a fourth width which is less than the third width, the step of chemical-mechanical polishing defining the inner upwardly projecting conductive mass into the shape of a ring.