Process for forming multilayer wiring

• US 5,498,768 A
• Filed: 07/06/1993
• Issued: 03/12/1996
• Est. Priority Date: 07/27/1988
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Kobayashi, Shigeru, Ishino, Masakazu, Tamaru, Tsuyoshi, Nishitani, Eisuke, Kasahara, Osamu, Nezu, Hiroki, Tsuzuku, Susumu
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/087,027
• Time in Patent Office: 980 Days
• Field of Search: 437/192, 437/937, 437/939, 437/946, 148/DIG. 17
• US Class Current: 438/644
• CPC Class Codes: C23C 16/0245 by etching with a plasma
• CPC Class Codes: C23C 16/045 Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/906 Cleaning of wafer as interim step

Abstract

The present invention relates to a method for filling small via holes provided to insulating film on a wafer to expose parts of the underlayer of the wafer by metal by means of CVD, and an apparatus therefor. The gist of the present invention lies in that, before CVD is conducted, a surface cleaning treatment of small via hole bottom underlayer surface and a stabilization treatment of insulating film surface activated thereby are carried out successively or simultaneously and optionally an anti-corrosive treatment is applied to underlayer surface, and then the CVD treatment is conducted without exposing the underlayer metal subjected to above treatments to the air. The present invention provides an effect of enabling via filling by metal which shows good selectivity and gives a low interfacial resistance between underlayer metal and filled metal.

Claims

1. A process for forming a multilayer wiring in a fabricated wafer, said multilayer wiring comprising a plurality of wirings stacked via silicon and oxygen-containing insulating layers each provided between one and another of said wirings, one of said wirings being electrically connected to another wiring through via-holes, which comprises the steps of:

(a) introducing into a pretreatment chamber said fabricated wafer having the wirings, one of which is covered thereon by the insulating layers except said via-holes, the surfaces of the wiring exposed at the via-holes being covered by a native oxide of the wiring;

(b) introducing a rare gas into said pretreatment chamber and then forming a plasma in said chamber by electric discharge to physically remove an amount of said oxide from the exposed surfaces due to the collision of plasma particles against the surfaces;

(c) introducing an etching gas into said chamber, then forming a plasma in said pretreatment chamber by electric discharge and introducing said fabricated wafer from step (b) into said plasma, thereby increasing the oxygen content of the surface of said insulating layers as reduced during the physical removal of the oxide in step (b) to restore the reduced oxygen/silicon ratio of the surface of the insulating layers, to that before the pretreatment of step (b);

(d) ceasing the introduction of both the rare gas and etching gas in said pretreatment chamber and then evacuating said pretreatment chamber;

(e) subjecting the exposed surfaces of the wiring to a treatment for corrosion prevention and transferring said fabricated wafer to an evacuated deposition chamber; and

,

(f) introducing a deposition material gas into said deposition chamber containing the corrosion-prevention treated wafer placed therein, and selectively depositing said material only on said exposed surfaces of the wiring in said via-holes to fill said via-holes with the deposited material; and

,

(g) preparing another wiring on said insulating layers.

2. The process according to claim 1, wherein said etching gas is a gas at least containing chlorine or a chlorine compound.

3. The process according to claim 1, wherein said treatment for corrosion prevention is carried out in said pretreatment chamber.

4. The process according to claim 1, wherein said treatment for corrosion prevention is carried out in a chamber separately provided, containing said fabricated wafer transferred thereto from said pretreatment chamber.

5. The process according to claim 1, wherein said treatment for corrosion prevention is carried out in said deposition chamber.

6. The process according to claim 1, wherein said treatment for corrosion prevention is carried out by heating said fabricated wafer under vacuum or in an atmosphere of one or more of nitrogen gas, hydrogen gas, and a rare gas at a higher wafer temperature than that used in the subsequent depositing step (f).

7. A process for forming a multilayer wiring in a fabricated wafer, said multilayer wiring comprising a plurality of wirings stacked via silicon and oxygen-containing insulating layers each provided between one and another of said wirings, one of said wirings being electrically connected to another wiring through via-holes, which comprises the steps of:

(a) introducing into a pretreatment chamber said fabricated wafer having the wirings, one of which is covered thereon by the insulating layers except said via-holes, the surfaces of the wiring exposed at the via-holes being covered by a native oxide of the wiring;

(b) introducing a rare gas into said pretreatment chamber, then forming a plasma in said chamber by electric discharge to physically remove an amount of said oxide from the exposed surfaces due to the collision of plasma particles against the surfaces, and ceasing the introduction of the rare gas in the pretreatment chamber;

(c) introducing an etching gas into said chamber, then forming a plasma in said pretreatment chamber by electric discharge and introducing said fabricated wafer from step (b) into said plasma, thereby increasing the oxygen content of the surface of said insulating layers as reduced during the physical removal of the oxide in step (b) to restore the reduced oxygen/silicon ratio of the surface of the insulating layers, to that before the pretreatment of step (b);

(d) ceasing the introduction of the etching gas in said pretreatment chamber and then evacuating said pretreatment chamber;

(e) subjecting the exposed surfaces of the wiring to a treatment for corrosion prevention and transferring said fabricated wafer to an evacuated deposition chamber; and

,

(f) introducing a deposition material gas into said deposition chamber containing the corrosion-prevention treated wafer placed therein, and selectively depositing said material only on said exposed surfaces of the wiring in said via-holes to fill said via-holes with the deposited material; and

,

(g) preparing another wiring on said insulating layers.

8. The process according to claim 7, wherein said etching gas is a gas at least containing chlorine or a chlorine compound.

9. The process according to claim 7, wherein said treatment for corrosion prevention is carried out in said pretreatment chamber.

10. The process according to claim 7, wherein said treatment for corrosion prevention is carried out in a chamber separately provided, containing said fabricated wafer transferred thereto from said pretreatment chamber.

11. The process according to claim 7, wherein said treatment for corrosion prevention is carried out in said deposition chamber.

12. The process according to claim 7, wherein said treatment for corrosion prevention is carried out by heating said fabricated wafer under vacuum or in an atmosphere of one or more of nitrogen gas, hydrogen gas, and a rare gas at a higher wafer temperature than that used in the subsequent depositing step (f).

13. A process for forming a multilayer wiring in a fabricated wafer, said multilayer wiring comprising a plurality of wirings stacked via silicon and oxygen-containing insulating layers each provided between one and another of said wirings, one of said wirings being electrically connected to another wiring through via-holes, which comprises the steps of:

(a) introducing into a pretreatment chamber said fabricated wafer having the wirings, one of which is covered thereon by the insulating layers except said via-holes, the surfaces of the wiring exposed at the via-holes being covered by a native oxide of the wiring;

(b) introducing a rare gas and an etching gas or an etching gas alone, forming a plasma of said gases or gas by electric discharge, and exposing said fabricated wafer to the plasma, to physically remove an amount of said oxide from the exposed surfaces due to the collision of plasma particles against the surfaces and chemically removing an amount of said oxide with radicals in said plasma, while simultaneously increasing the oxygen content of the surface of said insulating layer to restore the oxygen/silicon ratio of the surface of the insulating layer, which was reduced during the removal of the oxide film, to that before the pretreatment of step (a);

(c) ceasing the introduction of the rare gas and the etching gas or the etching gas alone in said pretreatment chamber and then evacuating said pretreatment chamber;

(d) subjecting the exposed surfaces of the wiring to a treatment for corrosion prevention and transferring said fabricated wafer to an evacuated deposition chamber; and

,

(e) introducing a deposition material gas into said deposition chamber containing the corrosion-prevention treated wafer placed therein, and selectively depositing said material only on said exposed surfaces of the wiring in said via-holes to fill said via-holes with the deposited material; and

,

(f) preparing another wiring on said insulating layers.

14. The process according to claim 13, wherein said etching gas is a gas at least containing chlorine or a chlorine compound.

15. The process according to claim 13, wherein said treatment for corrosion prevention is carried out in said pretreatment chamber.

16. The process according to claim 13, wherein said treatment for corrosion prevention is carried out in a chamber separately provided, containing said fabricated wafer transferred thereto from said pretreatment chamber.

17. The process according to claim 13, wherein said treatment for corrosion prevention is carried out in said deposition chamber.

18. The process according to claim 13, wherein said treatment for corrosion prevention is carried out by heating said fabricated wafer under vacuum or in an atmosphere of one or more of nitrogen gas, hydrogen gas, and a rare gas at a higher wafer temperature than that used in the subsequent depositing step (f).