Adaptive programming method for antifuse technology

• US 5,498,979 A
• Filed: 09/20/1994
• Issued: 03/12/1996
• Est. Priority Date: 09/03/1992
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Trimberger, Stephen M., Goetting, F. Erich, Parlour, David B., Young, Edel M.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): SANTAMAURO, JON P
• Application Number:
  US08/310,111
• Time in Patent Office: 539 Days
• Field of Search: 326/38-39, 326/9-10, 327/525, 340/825.83, 340/825.84, 340/825.87, 340/825.79, 340/827, 364/716, 364/488-491
• US Class Current: 326/38
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns

Abstract

For antifuse programmable integrated circuit devices, in particular FPGA devices, the invention allows for alternative routing around antifuses which fail to program. The chip architecture includes wiring segments and antifuses which together allow for alternative routes around every antifuse in the event of failure of that antifuse. The method includes programming the device under control of a computer which can recalculate routes in the event of an antifuse which fails to program. Preferably the initial routing distributes unused wiring segments through the chip to be available for routing around a failed antifuse. When a failure occurs, the method includes determining an alternative route around every failed antifuse. The alternative route may be established directly after the antifuse has failed or after all initially selected antifuses have been programmed. The method also includes swapping of logic cell inputs, logic cells, and/or logic blocks from their original layout to adapt to a failed antifuse without changing the timing of signals which would have used the failed antifuse.

Claims

1. A method of programming a programmable device having interconnect wiring segments and programmable elements which programmably connect said wiring segments to each other, said method comprising the steps of:

providing a design in machine readable form, said design comprising connections between selected nodes in said device;

for each of said connections, selecting active wiring segments and active programmable elements in said programmable device to implement said connection, thereby to form a route for said connection;

programming at least some of said active programmable elements;

if during programming any of said active programmable elements fails to become conductive, selecting from those programmable elements not yet programmed an alternative set of programmable elements to complete said connections;

programming said alternative set of programmable elements, thereby to form an implementation of said design.

2. A method as in claim 1 comprising the further step of leaving spare wiring segments and spare programmable elements not used initially for any of said connections.

3. A method as in claim 1 in which

said design comprises a logic design comprising both design elements and said connections, and

said device further comprises logic elements, said programmable elements programmably connecting said logic elements to said wiring segments,

said method comprising the further steps of:

selecting one of said logic elements to implement each of said design elements;

leaving spare logic elements not used initially for any of said design elements.

4. A method as in claim 1 in which

said design comprises a logic design comprising both design elements and said connections, and

said device further comprises logic elements grouped into blocks, said programmable elements programmably connecting said logic elements to said wiring segments,

said method comprising the further step of:

leaving spare blocks not used initially for any of said design elements.

5. A method as in claim 1 in which

said design comprises a logic design comprising both design elements and said connections, and

said device further comprises logic elements, said programmable elements programmably connecting said logic elements to said wiring segments,

said method comprising the further steps of:

selecting one of said logic elements to implement each of said design elements;

leaving spare logic element inputs not used initially in at least some of said logic elements.

6. A method as in claim 1 in which said active programmable elements are programmed in the order of time to spare for a path such that paths having the least time to spare in meeting a timing requirement are programmed first.

7. A method as in claim 1 in which said alternative set of programmable elements is selected such that paths selected after a programmable element failure have the same timing as corresponding paths selected before said programmable element failure.

8. A method as in claim 1 in which said alternative set of programmable elements is selected so that said implementation of said logic design meets the same timing requirements as would have been met if no programmable elements failed.

9. A method as in claim 1 in which said step of selecting an alternative set of programmable elements is performed after a first failed programmable element is found.

10. A method as in claim 1 in which

said design comprises a logic deign comprising both design elements and said connections, and

said device further comprises logic elements, said programmable elements programmably connecting said logic elements to said wiring segments,

said alternative set of programmable elements is selected to swap equivalent input ports of a logic element which will receive plural input signals, thereby avoiding said failed programmable element.

11. A method as in claim 1 in which all of said active programmable elements are programmed as part of a first programming step, and said alternative set of programmable elements are selected and programmed after said first programming step.

12. A method as in claim 1 in which said wiring segments comprise both horizontal and vertical wiring segments, and said programmable elements are positioned at intersections of said horizontal and vertical wiring segments, spare wiring segments being selected from both horizontal and vertical wiring segments.

13. A method as in claim 1 in which said alternative set of programmable elements is selected to swap equivalent wiring segments, thereby avoiding said failed programmable element.

14. A method of programming an antifuse programmable logic device having logic elements, interconnect wiring segments, and antifuses which programmably connect wiring segments to each other and to said logic elements, said method comprising the steps of:

providing a logic design in machine readable form, said logic design comprising design elements and connections for carrying a signal from an output terminal of one of said design elements to an input terminal of at least one of said design elements;

selecting one of said logic elements to implement at least one of said design elements;

for at least one of said connections, selecting active wiring segments and active antifuses in said antifuse programmable logic device to form a route from an output terminal of one of said design elements to an input terminal of at least one of said design elements;

selecting one of said logic elements to implement at least one of said design elements;

for said at least one of said connections, programming said active antifuses in order of signal flow from said output terminal of said one of said design elements to said input terminal of said at least one of said design elements;

if an antifuse fails to become conductive upon programming, for at least that connection of which said failed antifuse is a part, calculating an alternative route to complete that connection; and

continuing to program active antifuses in said alternative route in order of signal flow to said input terminal of said at least one of said design elements.