Intrusion detector test circuit which automatically disables a detected-event indicator

• US 5,499,012 A
• Filed: 03/30/1994
• Issued: 03/12/1996
• Est. Priority Date: 03/30/1994
• Status: Expired due to Term

• Current Assignee: C & K Systems, Inc. (Honeywell International Inc.)
• Original Assignee: C & K Systems, Inc. (Honeywell International Inc.)
• Inventors: Dorando, Dale, Tracy, Lawrence, Eggers, Frederick
• Primary Examiner(s): Crosland, Donnie L.
• Application Number:
  US08/219,783
• Time in Patent Office: 713 Days
• Field of Search: 340/514, 340/515, 340/506, 340/522, 340/539
• US Class Current: 340/514
• CPC Class Codes: G08B 29/14 checking the detection circuits

Abstract

An intrusion detector test circuit automatically disables a detected-event indicator from receiving sensing signals. A sensor generates a sensing signal in response to a detection of an installer testing the intrusion detector. An indictor means receives the sensing signals and generates detected-event indications in response to the sensing signals. A switch interposed between the sensor and the indicator receives the sensing signals. In a first state, the switch supplies the sensing signals to the indicator; in a second state, the switch means does not supply the sensing signals to the indicator. A first state setter sets the switch to the first state, and a second state setter automatically sets the switch to the second state after a lapse of a predetermined time period.

Claims

1. An intrusion detector test circuit for testing an intrusion detector, comprising:

sensing means for generating a sensing signal in response to a detection of an installer testing the intrusion detector;

indicating means for receiving said sensing signal and for generating a detected-event indication in response thereto;

switch means interposed between said sensing means and said indicating means for receiving said sensing signal and, in a first state, for supplying said sensing signal to said indicating means, and, in a second state, for not supplying said sensing signal to said indicating means;

first state setting means for setting said switch means to said first state; and

second state setting means for automatically setting said switch means to said second state after a lapse of a predetermined time period.

2. An intrusion detector test circuit as in claim 1, wherein said indicating means is a visual indicator.

3. An intrusion detector test circuit as in claim 1, wherein said indicating means is an audio indicator.

4. An intrusion detector test circuit as in claim 1, wherein said indicating means is a RF transmitter that generates an event indication by transmitting an RF signal.

5. An intrusion detector test circuit as in claim 1, wherein said first state setting means sets said switch means to said first state by applying a first switch state control signal to said switch means.

6. An intrusion detector test circuit as in claim 5, wherein said a predetermined time period begins responsive to a timeout trigger signal.

7. An intrusion detector test circuit as in claim 6, wherein said second state setting means sets said switch means to said second state by applying a second switch state control signal to said switch means.

8. An intrusion detector test circuit as in claim 6, wherein said first switch state control signal is said timeout trigger signal.

9. An intrusion detector test circuit as in claim 6, wherein the intrusion detector is housed within a housing and said intrusion detector test circuit further comprises:

a tamper switch means operable in two modes, actuated when said housing is removed and deactuated when said housing is replaced, wherein in a first mode actuating said tamper switch causes said intrusion detector to generate an alarm, and wherein in a second mode actuating said tamper switch causes said first state setting means to apply said first switch state control signal to said switch means.

10. An intrusion detector test circuit as in claim 9, wherein deactuating said tamper switch when said intrusion detector is in said second mode causes said timeout trigger signal.

11. An intrusion detector test circuit as in claim 1, further comprising:

lockout control means for disabling a lockout circuit when said lockout control means is in a first state and for automatically enabling the lockout circuit when said lockout control means is in a second state

wherein said first state setting means sets said lockout control means to said first state and said second state setting means automatically sets said lockout control means to said second state after said lapse of said a predetermined time period.

12. An intrusion detector test circuit for testing an intrusion detector, comprising:

sensing means for generating a sensing signal in response to a detection of an installer testing the intrusion detector;

indicating means for receiving said sensing signal and for generating a detected-event indication in response thereto;

switch means interposed between said sensing means and said indicating means for receiving said sensing signal and, in a first state, for supplying said sensing signal to said indicating means, and, in a second state, for not supplying said sensing signal to said indicating means; and

timer circuit means for setting said switch means to said first state and for setting said switch means to said second state automatically after a lapse of an predetermined time period, after said switch means is in said first state.

13. An intrusion detector test circuit as in claim 12, wherein

said timer circuit means comprises a capacitor, a first terminal of said capacitor switchably connected to a voltage source and a second terminal of said capacitor connected to ground, and a first resistor connected between said first terminal of said capacitor and ground, said first terminal of said first capacitor connected to said switch means

whereby said timer circuit means applies a voltage at said first terminal of said capacitor to said switch means, for setting said switch means to said first state upon said first terminal of said capacitor being connected to said voltage source, and for setting said switch means to said second state, after said first terminal of said capacitor being switchably disconnected from said voltage source, and the voltage at said first terminal of said capacitor being discharged through said first resistor, after said predetermined time period, said predetermined time period being determined by a resistance of said first resistor and a capacitance of said capacitor.

14. An intrusion detector test circuit as in claim 13, wherein

said timer circuit means further comprises a second resistor interposed between said first terminal of said capacitor and said switchably connected voltage source

whereby said timer circuit means applies a voltage at said first terminal of said capacitor to said switch means, for setting said switch means to said first state upon said first terminal of said capacitor being connected to said voltage source through said second resistor, after a time period determined by a resistance of said second resistor and said capacitance of said capacitor.

15. An intrusion detector test circuit for testing an intrusion detector, the intrusion detector being housed within a housing and having a sensing means for generating a sensing signal in response to a detection of an installer testing the intrusion detector, said intrusion detector test circuit comprising:

indicating means for receiving said sensing signal and for generating a detected-event indication in response thereto;

switch means interposed between said sensing means and said indicating means for receiving said sensing signal and, in a first state, for supplying said sensing signal to said indicating means, and, in a second state, for not supplying said sensing signal to said indicating means;

first state setting means for setting said switch means to said first state by applying a first switch state control signal to said switch means; and

second state setting means for automatically setting said switch means to said second state after a lapse of a predetermined time period by applying a second switch control signal after said lapse of said predetermined time period; and

tamper switch means operable in two modes, actuated when said housing is removed and aleactuated when said housing is replaced, wherein in a first mode actuating said tamper switch causes said intrusion detector to generate an alarm, and wherein in a second mode actuating said tamper switch causes said first state setting means to apply said first switch state control signal to said switch means.

16. An intrusion detector test circuit as in claim 15, wherein said a predetermined time period begins responsive to a timeout trigger signal.

17. An intrusion detector test circuit as in claim 16, wherein said first switch state control signal is said timeout trigger signal.

18. An intrusion detector test circuit as in claim 16, wherein deactuating said tamper switch causes said timeout trigger signal to be generated.

19. An intrusion detector test circuit as in claim 15, further comprising:

lockout control means for disabling a lockout circuit when said lockout control means is in a first state and for automatically enabling the lockout circuit when said lockout control means is in a second state

wherein said first state setting means sets said lockout control means to said first state and said second state setting means automatically sets said lockout control means to said second state after said lapse of said predetermined time period.