Multiplexed memory timing with block reset and secondary memory

• US 5,499,062 A
• Filed: 06/23/1994
• Issued: 03/12/1996
• Est. Priority Date: 06/23/1994
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Urbanus, Paul M.
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): Murrell, Jeffrey S.
• Application Number:
  US08/264,387
• Time in Patent Office: 628 Days
• Field of Search: 348/571, 348/718, 348/761, 348/762, 348/764, 348/759, 348/766, 348/771, 345/84, 345/85, 345/86
• US Class Current: 348/771
• CPC Class Codes: G09G 2300/0804 Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0857 Static memory circuit, e.g. flip-flop
• CPC Class Codes: G09G 2310/061 for resetting or blanking
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/346 based on modulation of the reflection angle, e.g. micromirrors micromirrors devices per se G02B26/0833

Abstract

A spatial light modulator array with adaptable multiplexed memory architecture. The modulator has an array of individually controllable pixels, where a predetermined number of pixels are assigned to a memory cell (16). The memory cell receives data from an input bus (14). On a signal (22), the memory cell transfers its data to a secondary memory (18), and to the activation circuitry (20) of one of its assigned pixels. On a second signal, the pixel responds to the data on the activation circuitry. When the display time of the data is less than the load time for the memory cell, the secondary memory is set with a second signal (24) so as to make the pixel dark and another control signal makes the pixels respond to the memory. In this way, the load time is lengthened and the data rate remains relatively low, even though the number of bits of intensity may not be the same as the number of bits of intensity used to determine the number of pixels assigned to each memory cell.

Claims

1. A spatial light modulator with improved data loading, comprising:

a. an array of individually addressable pixels, each pixel consisting of;

i. an active area; and

ii. activation circuitry, where said activation circuitry receives data, said data causing said active area to assume one of two states;

b. memory cells in electrical connection with said pixels, wherein at least two unique pixels are in dedicated connection with each one of each memory cell;

c. additional circuitry between said memory cell and said pixels such that said additional circuitry receives said data from a memory cell before said activation circuitry and allows said memory cell to receive new data, wherein said additional circuitry is capable of receiving independent control signals.

2. The modulator of claim 1 wherein said pixels are digital mirror devices.

3. The modulator of claim 1 wherein said pixels are liquid crystal cells.

4. The modulator of claim 1 wherein said pixels are actuated mirror arrays.

5. The modulator of claim 1 wherein said activation circuitry is at least one electrode.

6. The modulator of claim 1 wherein said additional circuitry is a data latch.

7. A method for improved data loading of a spatial light modulator, comprising:

a. sending a first data signal to an array of first memory cells, wherein each said first memory cell is assigned at least two unique, individually addressable pixels of said spatial light modulator;

b. receiving said first data signal at said array of first memory cells;

c. sending a transfer control signal to said array of first memory cells causing each of said first memory cells to transfer said first data signal to a second memory cell;

d. sending said first data signal from said second memory cell to activation circuitry in each of said pixels;

e. sending a second control signal causing said pixels to respond to said first data signal;

f. selectively sending a third control signal, causing selected ones of said pixels to stop responding to said first data signal, while receiving a second data signal at each of said first memory cells of said selective ones of said pixels.