Method for generating logic modules from a high level block diagram

• US 5,499,192 A
• Filed: 06/30/1994
• Issued: 03/12/1996
• Est. Priority Date: 10/30/1991
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Seidel, Jorge P., Knapp, Steven K., Kelem, Steven H.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US08/268,884
• Time in Patent Office: 621 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/492, 364/493, 364/578
• US Class Current: 716/102
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A set of module generators produce optimized implementations of particular circuit logic arithmetic functions for Field Programmable Gate Arrays (FPGAs) or other digital circuits. The module generators allow a circuit designer to spend more time actually designing and less time determining device-specific implementation details. The module generators accept a high level block diagram schematic of the circuit and automatically perform the detailed circuit design, including propagation of data types (precision and type) through the circuit, and low level circuit design optimization using a library of arithmetic and logic functions. The module generators are particularly useful for designs using field programmable gate arrays because of their unique architectures and ability to implement complex functions.

Claims

1. A method of designing a digital circuit comprising the steps of:

capturing a digital circuit design as a plurality of high level arithmetic and logical functions;

providing a library of arithmetic and logical components corresponding to the plurality of high level arithmetic and logical functions, wherein the arithmetic and logical components are adaptable to a plurality of data types and precisions, wherein said data types include encoding information;

assigning a component from the library to each function;

inputting a user-selected data type and precision in the digital circuit;

propagating the selected data type and precision through the digital circuit; and

adapting at least one component as a result of the step of propagating.

2. The method of claim 1, further comprising a step of including components that are not altered in the step of adapting.

3. The method of claim 1, further comprising step, before the step of propagating, of converting the captured design to a net list.

4. The method of claim 1, further including a step of:

optimizing a digital design for an architecture.

5. The method of claim 4, wherein the step of optimizing includes assigning a portion of the digital design to a section of afield programmable gate array.

6. The method of claim 4, further including a step of expanding the plurality of high level arithmetic and logical functions to their full width.

7. The method of claim 6, wherein the step of expanding uses a hard macro

8. The method of claim 4, wherein the step of optimizing includes allocating clock signals to primary buffers.

9. The method of claim 4, wherein the step of optimizing includes allocating set/reset signals.

10. The method of claim 4, wherein the step of optimizing includes allocating registers.

11. The method of claim 1, wherein the step of adapting comprises the steps of:

expressing a plurality of input buffer and output buffer pairs with one symbol; and

expanding the one symbol into at least one or more input buffer and output buffer pairs.

12. The method of claim 1, wherein the step of adapting includes the steps of:

providing a circuit module which is a tree comparator; and

selecting internal elements for the tree comparator which makes at least two bit comparisons simultaneously and which is organized hierarchically.

13. The method of claim 1, wherein the step of adapting includes the steps of:

providing a circuit module which is a wired-and comparator; and

selecting internal elements for the wired-and comparator in which a plurality of compare elements are logically connected by AND functions.

14. The method of claim 1, wherein the step of adapting includes the step of specifying all input lines to the digital circuit with one symbol.

15. The method of claim 1, wherein the step of adapting includes the step of specifying a group of output buffers and output pads from the digital circuit with one symbol.

16. The method of claim 1, wherein the step of adapting includes the steps of:

expressing a plurality of bidirectional buffers and input/output pads with one symbol; and

expanding the one symbol to one or more single bidirectional buffers and input/output pads.