Semiconductor memory device having improved isolation between electrodes, and process for fabricating the same
First Claim
1. A semiconductor memory device having a plurality of capacitors arranged in parallel, wherein each capacitor include at least one electrode, said memory device comprising:
- a first insulator arranged between the electrodes of said capacitors; and
a second insulator acting as dielectrics of said capacitors,wherein said first insulator is a modified portion of said second insulator.
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Accused Products
Abstract
With recent decreases in the size of semiconductor memories, isolation problems typically arise during fabrication of a capacitor for a high-capacity semiconductor memory device. To overcome this, arrangements are provided to improve the isolation between capacitor elements even if those elements are extremely close together. For example, if a material such as platinum is used as a capacitor bottom electrode, a thin layer of titanium oxide can be deposited before forming the platinum, to provide a structure in which the titanium oxide is on the bottom portion of the trench. A high-dielectric-constant insulator is then formed over that structure by the Chemical Vapor Deposition. The high-dielectric-constant insulator has a composition which satisfies the stoichiometric composition over the platinum and which has more titanium atoms than those of the stoichiometric composition on the trench bottom. The resulting non-stoichiometric composition layer formed on the trench bottom has a low dielectric constant and a high insulation to maintain electric insulation between adjoining bottom capacitor electrodes. Because of a low crystallization, moreover, a layer having a planarized morphology is formed.
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Citations
32 Claims
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1. A semiconductor memory device having a plurality of capacitors arranged in parallel, wherein each capacitor include at least one electrode, said memory device comprising:
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a first insulator arranged between the electrodes of said capacitors; and a second insulator acting as dielectrics of said capacitors, wherein said first insulator is a modified portion of said second insulator. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16)
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15. A semiconductor memory device as set forth in claim wherein said first insulator is formed by Sol-Gel.
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17. A semiconductor memory device comprising:
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an insulator formed over a semiconductor active layer, which active layer includes a device for driving a capacitor; a bottom electrode of the capacitor formed over a predetermined region of said insulator and having a predetermined shape; a crystalline insulator formed continuously over an exposed surface of said insulator and said bottom electrode; and an upper electrode of the capacitor formed over said crystalline insulator, wherein the portion of said insulator, over which said bottom electrode is not formed, has a modified surface, and wherein the crystallinity and dielectric constant of said crystalline insulator formed over said modified surface are lower than the crystallinity and dielectric constant of said crystalline insulator formed over said bottom electrode. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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28. A semiconductor memory device comprising:
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an active device layer; a first insulator formed over said active device layer; a second insulator having a low dielectric constant formed over said first insulator; a plurality of bottom capacitor electrodes formed over said second insulator, said bottom capacitor electrodes being spaced apart from one another on said second insulator; a high dielectric constant layer formed over said bottom capacitor electrodes and over portions of said second insulator located between said bottom capacitor electrodes, wherein said second insulator and said high dielectric constant layer include materials that will react with one another at said portions of said second insulator located between said bottom capacitor electrodes to form a modified structure having a low dielectric constant and a high breakdown voltage between the bottom capacitor electrodes; and a top capacitor electrode formed over said high dielectric constant layer over said bottom capacitor electrodes, and also formed over said portions of said modified structure located between said bottom capacitor electrodes. - View Dependent Claims (29, 30)
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31. A semiconductor memory device having a plurality of capacitors arranged in parallel, wherein each capacitor includes at least one electrode, said memory device comprising:
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a first insulator arranged between the electrodes of said capacitors, a second insulator acting as dielectrics of said capacitors, wherein said first insulator and said second insulator are formed at the same time, and wherein said first insulator has a smaller dielectric constant than that of said second insulator. - View Dependent Claims (32)
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Specification