Semiconductor memory device having improved isolation between electrodes, and process for fabricating the same

• US 5,499,207 A
• Filed: 07/28/1994
• Issued: 03/12/1996
• Est. Priority Date: 08/06/1993
• Status: Expired due to Term

• Current Assignee: PS4 Luxco S.a.r.l.
• Original Assignee: Hitachi, Ltd.
• Inventors: Miki, Hiroshi, Tachi, Shinichi, Ohji, Yuzuru
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Hoang, Huan
• Application Number:
  US08/281,568
• Time in Patent Office: 593 Days
• Field of Search: 365/149, 365/145, 365/189.01, 365/174, 257/295, 257/306, 257/310
• US Class Current: 365/149
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H10B 12/318 the storage electrode having multiple segments
• CPC Class Codes: Y10S 438/974 Substrate surface preparation

Abstract

With recent decreases in the size of semiconductor memories, isolation problems typically arise during fabrication of a capacitor for a high-capacity semiconductor memory device. To overcome this, arrangements are provided to improve the isolation between capacitor elements even if those elements are extremely close together. For example, if a material such as platinum is used as a capacitor bottom electrode, a thin layer of titanium oxide can be deposited before forming the platinum, to provide a structure in which the titanium oxide is on the bottom portion of the trench. A high-dielectric-constant insulator is then formed over that structure by the Chemical Vapor Deposition. The high-dielectric-constant insulator has a composition which satisfies the stoichiometric composition over the platinum and which has more titanium atoms than those of the stoichiometric composition on the trench bottom. The resulting non-stoichiometric composition layer formed on the trench bottom has a low dielectric constant and a high insulation to maintain electric insulation between adjoining bottom capacitor electrodes. Because of a low crystallization, moreover, a layer having a planarized morphology is formed.

Claims

1. A semiconductor memory device having a plurality of capacitors arranged in parallel, wherein each capacitor include at least one electrode, said memory device comprising:

a first insulator arranged between the electrodes of said capacitors; and

a second insulator acting as dielectrics of said capacitors,

wherein said first insulator is a modified portion of said second insulator.

2. A semiconductor memory device as set forth in claim 1, characterized in that said first insulator is interposed between the electrodes of said capacitors and a third insulator for insulating said capacitors from other electric circuits.

3. A semiconductor memory device as set forth in claim 1, characterized in that said second insulator is formed by Chemical Vapor Deposition.

4. A-semiconductor memory device as set forth in claim 1, characterized in that the dielectric constant of said second insulator at a portion contacting with said first insulator is no more than 10% of the dielectric constant of said second insulator over said electrode.

5. A semiconductor memory device as set forth in claim 1, characterized in that said first insulator is composed mainly of an oxide of any one of Ta, Nb, Ti, Zr and Hf.

6. A semiconductor memory device as set forth in claim 1, characterized in that said first insulator is formed by Chemical Vapor Deposition or Sol-Gel.

7. A semiconductor memory device as set forth in claim 1, characterized in that said at least one electrode of each capacitor is comprised mainly of platinum, palladium or nickel.

8. A semiconductor memory device as set forth in claim 1, wherein said second insulator is formed on a side wall of one of said electrodes.

9. A semiconductor memory device according to claim 1, wherein the first insulator is formed relative to the electrodes of the capacitors and relative to the second insulator so that characteristics of the first insulator can be selectively changed in a self-aligned manner without deteriorating characteristics of the second insulator.

10. A semiconductor memory device as set forth in claim 1, wherein said first insulator is planarized.

11. A semiconductor memory device as set forth in claim 10, wherein said first insulator is interposed between the electrodes of said capacitors and a third insulator for insulating said capacitors from other electric circuits.

12. A semiconductor memory device as set forth in claim 10, wherein said second insulator is formed by Chemical Vapor Deposition.

13. A semiconductor memory device as set forth in claim 10, wherein the dielectric constant of said first insulator is not more than 10% of the dielectric constant of said second insulator.

14. A semiconductor memory device as set forth in claim 10, wherein said first insulator is composed mainly of an oxide of any one of Ta, Nb, Ti, Zr, and Hf.

16. A semiconductor memory device as set forth in claim 10, wherein said at least one electrode of each capacitor is comprised mainly of platinum, palladium or nickel.

15. A semiconductor memory device as set forth in claim wherein said first insulator is formed by Sol-Gel.

17. A semiconductor memory device comprising:

an insulator formed over a semiconductor active layer, which active layer includes a device for driving a capacitor;

a bottom electrode of the capacitor formed over a predetermined region of said insulator and having a predetermined shape;

a crystalline insulator formed continuously over an exposed surface of said insulator and said bottom electrode; and

an upper electrode of the capacitor formed over said crystalline insulator,

wherein the portion of said insulator, over which said bottom electrode is not formed, has a modified surface, and wherein the crystallinity and dielectric constant of said crystalline insulator formed over said modified surface are lower than the crystallinity and dielectric constant of said crystalline insulator formed over said bottom electrode.

18. A semiconductor memory device as set forth in claim 17, characterized in that said crystalline insulator contains barium titanate or lead titanate.

19. A semiconductor memory device as set forth in claim 17, characterized in that said modified surface of said insulator is made of silicon dioxide, and in that said modified surface has a smaller oxidation number than portions of the silicon dioxide that are not modified.

20. A semiconductor memory device as set forth in claim 17, characterized in that said modified surface is an ion-implanted layer.

21. A semiconductor memory device as set forth in claim 17, characterized in that said modified surface contains more silicon than portions of the insulator other than said modified surface.

22. A semiconductor memory device as set forth in claim 17, characterized in that the insulator having said modified surface is made of silicon dioxide, and in that said modified surface is formed by reducing the amount of silicon dioxide.

23. A semiconductor memory device as set forth in claim 17, characterized in that said semiconductor active layer is a semiconductor substrate on which metal oxide semiconductor transistors are formed.

24. A semiconductor memory device as set forth in claim 17, wherein the dielectric constant of said crystalline insulator formed over said modified surface is not more than 10% of the dielectric constant of said crystalline insulator formed over said bottom electrode.

25. A-semiconductor memory device as set forth in claim 17, wherein said crystalline insulator is composed mainly of an oxide of any one of Ta, Nb, Ti, Zr, and Hf.

26. A semiconductor memory device as set forth in claim 17, wherein said crystalline insulator is formed by Chemical Vapor Deposition or Sol-Gel.

27. A semiconductor memory device as set forth in claim 17, wherein said at least one electrode of said capacitor is comprised mainly of platinum, palladium or nickel.

28. A semiconductor memory device comprising:

an active device layer;

a first insulator formed over said active device layer;

a second insulator having a low dielectric constant formed over said first insulator;

a plurality of bottom capacitor electrodes formed over said second insulator, said bottom capacitor electrodes being spaced apart from one another on said second insulator;

a high dielectric constant layer formed over said bottom capacitor electrodes and over portions of said second insulator located between said bottom capacitor electrodes, wherein said second insulator and said high dielectric constant layer include materials that will react with one another at said portions of said second insulator located between said bottom capacitor electrodes to form a modified structure having a low dielectric constant and a high breakdown voltage between the bottom capacitor electrodes; and

a top capacitor electrode formed over said high dielectric constant layer over said bottom capacitor electrodes, and also formed over said portions of said modified structure located between said bottom capacitor electrodes.

29. A semiconductor memory device according to claim 28, wherein said second insulator comprises titanium dioxide, and wherein said high dielectric constant layer comprises PZT.

30. A semiconductor memory device according to claim 28, wherein said modified structure is a pyrochlore structure.

31. A semiconductor memory device having a plurality of capacitors arranged in parallel, wherein each capacitor includes at least one electrode, said memory device comprising:

a first insulator arranged between the electrodes of said capacitors,

a second insulator acting as dielectrics of said capacitors,

wherein said first insulator and said second insulator are formed at the same time, and wherein said first insulator has a smaller dielectric constant than that of said second insulator.

32. A semiconductor memory device according to claim 31, wherein the first insulator is formed relative to the electrodes of the capacitors and relative to the second insulator so that characteristics of the first insulator can be selectively changed in a self-aligned manner without deteriorating characteristics of the second insulator.