Oscillator circuit generating a clock signal having a temperature dependent cycle and a semiconductor memory device including the same

• US 5,499,214 A
• Filed: 06/10/1994
• Issued: 03/12/1996
• Est. Priority Date: 06/28/1993
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Kajimoto, Takeshi, Mori, Shigeru, Hayashikoshi, Masanori
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): LE, VU ANH
• Application Number:
  US08/257,845
• Time in Patent Office: 641 Days
• Field of Search: 365/211, 365/222, 365/225.7, 327/83, 327/88, 327/262, 327/291, 327/108
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/354 Astable circuits

Abstract

In a semiconductor memory device, a constant voltage is applied to a resistor having a positive temperature coefficient, whereby a first reference current flowing through that resistor is converted into a voltage by a resistor. That voltage is converted into a second reference current by a P channel MOS transistor, whereby a second current of a value equal to the value of the second reference current flows through each of a plurality of inverters by a current mirror circuit. These inverters are connected in a ring manner to form a ring oscillator. The first reference current becomes lower as the operating temperature rises, whereby the second reference current increases. As a result, the oscillator cycle of the ring oscillator becomes shorter as the operating temperature rises.

Claims

1. A semiconductor memory device comprising:

a memory cell array including a plurality of memory cells requiring a refresh operation,

an oscillator circuit including

reference current generation means for generating a reference current varying in response to an operating temperature, and

oscillator means for generating a clock signal having its cycle varying in response to said reference current, and

refresh means responsive to said clock signal for carrying out a refresh operation for said plurality of memory cells.

2. A semiconductor memory device comprising:

(a) a memory cell array including a plurality of memory cells requiring a refresh operation,

(b) an oscillator circuit including

reference current generation means including

potential generation means for generating an output potential varying in response to an operating temperature, and

voltage-current conversion means for generating a reference current varying in response to said output potential, and

oscillator means including an odd number of a plurality of inverter means connected in a ring manner, and means responsive to said reference current for supplying a charge current and/or a discharge current from an output node of at least one of said plurality of inverter means to an input node of the inverter means having an input node connected to said output node, said oscillator means providing a clock signal from an output node of the inverter means of the last stage, and

(c) refresh means responsive to said clock signal for carrying a refresh operation for said plurality of memory cells.

11. The semiconductor memory device according to claim 2, further comprising:

waveform shaping means for receiving said clock signal from said oscillator means and shaping the waveform thereof.

12. The semiconductor memory device according to claim 11, wherein said waveform shaping means comprises

first waveform shaping inverter means including

a first input node for receiving said clock signal from said oscillator means,

a first output node,

two first P channel transistors connected in series between a first power supply potential node and said first output node, and

two first N channel transistors connected between said first output node and a second power supply potential node,

wherein a gate electrode of one of said two first P channel transistors is connected to said first input node, and a gate electrode of the other of said two first P channel transistors is connected to an output node of one inverter means in a stage other than the last stage in said oscillator means, and a gate electrode of one of said two first N channel transistors is connected to said first input node, and a gate electrode of the other of said two first N channel transistors is connected to an output node of said one inverter means,

a second waveform shaping inverter means including

a second input node connected to said first output node of said first waveform shaping inverter means,

a second output node for providing a clock signal having its waveform shaped,

two second P channel transistors connected in series between said first power supply potential node and said second output node, and

two second N channel transistors connected between said second output node and said second power supply potential node,

wherein a gate electrode of one of said two second P channel transistors is connected to said second input node, and a gate electrode of the other of said two second P channel transistors is connected to an input node of said one inverter means, and a gate electrode of one of said two second N channel transistors is connected to said second input node, and a gate electrode of the other of said two second N channel transistors is connected to an input node of said one inverter means.

13. The semiconductor memory device according to claim 2, wherein said oscillator means receives a self refresh signal for providing said clock signal when said self refresh signal indicates execution of a self refresh operation, and for suppressing output of said clock signal when said self refresh signal does not indicate execution of the self refresh operation.

3. A semiconductor memory device comprising:

a memory cell array including a plurality of memory cells requiring a refresh operation,

an oscillator circuit including

reference current generation means having a reference transistor in which a reference current varying in response to an operating temperature flows, and

oscillator means including an odd number of a plurality of inverter means connected in ring manner, wherein each of said plurality of inverter means comprises an input node, an output node, a first transistor connected between a first power supply potential node and said output node and having a control electrode connected to said input node, and a second transistor connected between said output node and a second power supply potential node, and having a control electrode connected to said input node, wherein at least one of said plurality of inverter means further includes a control transistor forming a current mirror circuit with said reference transistor, and connected between said output node and said second power supply potential node, in series with said second transistor, said oscillator means providing a clock signal from the output node of an inverter means of the last stage, and

refresh means responsive to said clock signal for carrying out a refresh operation for said plurality of memory cells.

4. A semiconductor memory device comprising:

a memory cell array including a plurality of memory cells requiring a refresh operation,

an oscillator circuit including

reference current generation means having a reference transistor in which a reference current varying in response to an operating temperature flows, and

oscillator means including an odd number of a plurality of inverter means connected in a ring manner, wherein each of said plurality of inverter means comprises an input node, an output node, a first transistor connected between a first power supply potential node and said output node, and having a control electrode connected to said input node, and a second transistor connected between said output node and a second power supply potential node, and having a control electrode connected to said input node, wherein at least one of said plurality of inverter means further includes a control transistor forming a current mirror circuit with said reference transistor, connected between said first power supply potential node and said output node, in series with said first transistor, said oscillator means providing a clock signal from the output node of an inverter means of the last stage, and

refresh means responsive to said clock signal for carrying out a refresh operation for said plurality of memory cells.

5. A semiconductor memory device comprising:

a memory cell array including a plurality of memory cells requiring a refresh operation,

an oscillator circuit including

reference current generation means, wherein said reference current generation means includes a reference P channel transistor in which a reference current flows varying in response to an operating temperature, and a reference N channel transistor in which a reference current flows varying in response to an operating temperature, and

oscillator means including an odd number of a plurality of inverter means connected in a ring manner, each of said plurality of inverter means including an input node, an output node, a P channel transistor, connected between a first power supply potential node and said output node, and having a control electrode connected to said input node, and an N channel transistor, connected between said output node and a second power supply potential node, having a control electrode connected to said input node, wherein at least one of said plurality of inverter means further includes a control P channel transistor forming a current mirror circuit with said reference P channel transistor, connected between said first power supply potential node and said output node, in series with said P channel transistor, and a control N channel transistor forming a current mirror circuit with said reference N channel transistor, connected between said output node and said second power supply potential node, in series with said N channel transistor, said oscillator means providing a clock signal from an output node of the inverter means of the last stage,

refresh means responsive to said clock signal for carrying out a refresh operation for said plurality of memory cells.

9. The semiconductor memory device according to claim 5, wherein each of said plurality of memory cells comprises

one transistor element, and

one capacitor element,

wherein said reference current generation means comprises

a reference capacitor element having a first and a second electrode, and having said first electrode connected to one electrode of said capacitor element of a memory cell, and

a supply transistor connected between said second electrode of said reference capacitor element and said first power supply potential node for supplying a current to said second electrode of said reference capacitor element,

wherein said reference current flows in said reference P and N channel transistors in response to a current flowing in said supply transistor.

10. The semiconductor memory device according to claim 5, wherein each of said plurality of memory cells comprises

one transistor element, and

one capacitor element,

wherein said reference current generation means comprises

a diode element having a PN junction of a configuration and size similar to those of said transistor element, and

a supply transistor connected between an electrode of said diode element and said first power supply potential node for supplying a current to said electrode of said diode element,

wherein said reference current flows in said reference P and N channel transistors in response to a current flowing in said supply transistor.

6. A semiconductor memory device, comprising:

a memory cell array including a plurality of memory cells requiring a refresh operation;

an oscillator circuit including

reference current generation means, wherein said reference current generation means includes a reference P channel transistor in which a reference current flows varying in response to an operating temperature, and a reference N channel transistor in which a reference current flows varying in response to an operating temperature, and

oscillator means including an odd number of a plurality of inverter means connected in a ring manner, each of said plurality of inverter means including an input node, an output node, a P channel transistor, connected between a first power supply potential node and said output node, and having a control electrode connected to said input node, and an N channel transistor, connected between said output node and a second power supply potential node, having a control electrode connected to said input node, wherein at least one of said plurality of inverter means further includes a control P channel transistor forming a current mirror circuit with said reference P channel transistor, connected between said first power supply potential node and said output node, in series with said P channel transistor, and a control N channel transistor forming a current mirror circuit with said reference N channel transistor, connected between said output node and said second power supply potential node, in series with said N channel transistor, said oscillator means providing a clock signal from an output node of the inverter means of the last stage, and

a refresh means responsive to said clock signal for carrying out a refresh operation for said plurality of memory cells;

wherein said reference current generation means comprises

potential generation means for generating an output potential varying in response to an operating temperature, and

voltage-current conversion means for generating a current varying in response to said output potential, and

wherein said reference current flows in said reference P and N channel transistors in response to said current generated by said voltage-current conversion means.

7. The semiconductor memory device according to claim 6, wherein said potential generation means comprises resistor means having a positive temperature coefficient, connected between a node for providing said output potential and said first power supply potential node.

8. The semiconductor memory device according to claim 7, wherein said resistor means comprises

a plurality of resistance elements having a positive temperature coefficient, and

a plurality of program elements provided corresponding to said plurality of resistance elements for activating and deactivating a corresponding resistance element.