Method and apparatus for test generation and fault simulation for sequential circuits with embedded random access memories (RAMs)

• US 5,499,249 A
• Filed: 05/31/1994
• Issued: 03/12/1996
• Est. Priority Date: 05/31/1994
• Status: Expired due to Term

• Current Assignee: AT&T IPM Corp. (AT&T, Inc.)
• Original Assignee: AT&T Corporation (AT&T, Inc.)
• Inventors: Chakraborty, Tapan J., Agrawal, Vishwani D.
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US08/251,550
• Time in Patent Office: 651 Days
• Field of Search: 371/21.1, 371/21.2, 371/21.6, 371/22.2, 371/23, 371/25.1
• US Class Current: 714/736
• CPC Class Codes: G01R 31/318342 by preliminary fault modelling, e.g. analysis, simulation
• CPC Class Codes: G01R 31/318392 for sequential circuits G01R31/318544 takes precedence
• CPC Class Codes: G11C 29/10 Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns

Abstract

Testing of a sequential circuit (10) containing at least one embedded RAM (16) is accomplished by first generating a set of sequential vectors and then applying the vectors in sequence to a set of primary circuit inputs (PO_o -PO_j). The vectors are generated such that upon application to the circuit, the vectors excite potential faults at nodes (A) upstream of the RAM and propagate the effects of the faults through the RAM to the primary circuit outputs (PO_o -PO_j). Also, the test vectors serve to excite faults downstream of the RAM by propagating values through the RAM needed to excite the downstream faults. The fault effects (if any) that propagate to the circuit primary outputs are compared to a set of reference values to determine if any faults are present.

Claims

1. A method for testing a sequential circuit, including a least one sequential element and at least one embedded RAM linked to said one sequential element via a propagation path that includes at least one node and which extends from one of a set of primary circuit inputs through the RAM to one of a set of primary circuit outputs, comprising the steps of:

generating at least one sequence of test vectors for application to the primary inputs of the circuit to cause a fault at the node to be excited and to cause its effect to propagate through the RAM to said one of said primary circuit outputs when the node is upstream of the RAM and to cause the fault to be excited through the RAM when the node is downstream thereof, and to cause the fault'"'"'s effect to be propagated to said one of said primary outputs;

applying the sequence of test vectors to the circuit at its primary inputs to cause the circuit to generate response signals at its primary outputs; and

comparing the responses at the circuit outputs to a set of reference values to determine if any differences exist therebetween.

2. The method according to claim 1 wherein the test vectors are generated such that upon application to the sequential circuit, the test vectors cause the RAM to undergo a data transfer operation (i.e., a read or write operation) to cause a fault effect present at an input of the RAM to propagate to an output of the RAM.

3. The method according to claim 1 wherein the test vectors are generated to cause the RAM to execute a prescribed sequence of read and write operations so a predetermined logic value needed to excite a node downstream of the RAM propagates through the RAM to said node to excite it.

4. The method according to claim 3 wherein the test vectors are generated by effecting backward fault effect propagation through the RAM by:

(a) selecting an output terminal of the RAM where a prescribed data value would be propagated from an input of the RAM;

(b) holding each value on each address line of the RAM to a controllable value if the original value is unknown both in a current time frame and in a time frame previous to the current frame;

(c) setting said input value of said RAM with said prescribed data value at said time frame previous to the current frame;

(d) placing a prescribed logic value on a read/write line of the RAM to cause the RAM to undergo a write operation in the time frame previous to the current time frame and to cause the RAM to undergo a read operation in the current time frame, thereby causing the prescribed data value to appear on said RAM output line;

(e) backtracking to an alternative choice if any conflict occurred during steps (b)-(d), provided that an alternative choice exits, otherwise dropping the fault from consideration.

5. The method according to claim 1 further including the steps of:

(a) simulating a set of faults for detection by the test vectors;

(b) dynamically recording values in each said embedded RAM which are associated with faults not detected by said test vectors, together with information as to where such faulty values were found in each RAM and information identifying the RAM.

6. The method according to claim 1 wherein each embedded RAM is itself tested by the steps of:

sequentially applying a separate one of a set of address values to each of a set of address lines of each RAM and applying a read/write value to a read/write line of the RAM by shifting at least one scan vector through a chain of flip-flops each connected to the other and each connected to one of the address lines and the read/write line, respectively;

propagating data values from the primary inputs of the sequential circuit to each of a set of data inputs of the RAM for writing into the RAM; and

propagating each of a second set of data values from the primary inputs of the sequential circuit to cause each of a set of data values present at a separate one of a set of RAM outputs to the primary circuit outputs.