Method and apparatus for a multiprocessor resource lockout instruction

• US 5,499,356 A
• Filed: 12/28/1993
• Issued: 03/12/1996
• Est. Priority Date: 12/29/1989
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: CRAY Incorporated (Hewlett-Packard Enterprise Company)
• Inventors: Phelps, Andrew E., Spix, George A., Wilson, Jimmie R., Eckert, Roger E., Hessel, Richard E.
• Primary Examiner(s): Robertson, David L.
• Application Number:
  US08/173,923
• Time in Patent Office: 805 Days
• Field of Search: 395/400, 395/425, 395/474, 395/479, 395/481, 395/482, 395/490
• US Class Current: 711/152
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/8076 Details on data register access
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 2209/521 Atomic
• CPC Class Codes: G06F 8/433 Dependency analysis; Data or control flow analysis
• CPC Class Codes: G06F 8/45 Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30069 Instruction skipping instructions, e.g. SKIP
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30141 Implementation provisions of register files, e.g. ports
• CPC Class Codes: G06F 9/30149 of variable length instructions
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 : Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/526 : Mutual exclusion algorithms

Abstract

A method and apparatus for providing a resource lockout mechanism in a shared memory, multiprocessor system that is capable of performing both a read and write operation during the same memory operation. The load and flag instruction of the present invention can execute a read operation, followed by a write operation of a preselected flag value to the same memory location during the same memory operation. The load and flag instruction is particularly useful as a resource lockout mechanism for use in Monte Carlo applications.

Claims

1. In a computer system a method of protecting data accessed by more than one requestor the method comprising the steps of:

(a) defining a set of data values and a set of lock values, wherein the sets of data values and lock values are mutually exclusive;

(b) reading a protected memory location, wherein the step of reading the protected memory location comprises atomically swapping a lock value selected from the set of lock values with information at the protected memory location;

(c) determining whether the information read from the protected memory location is within the set of data values; and

(d) if the information read from the protected memory location is within the set of data values, then operating on the information to form a result, else repeating steps (b)-(d).

2. The method according to claim 1 wherein the method further comprises the step of:

(e) if the data read from the protected memory location is within the set of data values, then storing the result to the protected memory location.

3. The method according to claim 1 wherein the step (a) of defining a lock value comprises determining if the protected memory location has been designated as containing a floating point number and, if so, defining one of the set of lock values to a floating point not-a-number.

4. The method according to claim 1 wherein the step (a) of defining a lock value comprises defining one of the set of lock values to hexadecimal FFF4000000000000.

5. The method according to claim 1 wherein the step (d) of repeating comprises waiting a period of time before executing step (b).

6. A resource-lockout apparatus for a computer system having a shared memory, wherein a plurality of requestors may each request access to a selected memory location in the shared memory, and wherein a set of data values and a set of defined flag values are defined, wherein the set of data values and the set of defined flag values are mutually exclusive, the resource-lockout apparatus comprising:

(a) means for atomically swapping a lock value selected from the set of lock values with information at the protected memory location;

(b) means for determining whether the information read from the protected memory location is within the set of data values;

(c) means for operating on the information to form a result if the information read from the protected memory location is within the set of data values; and

(d) means for transferring control to means (a) if the information read from the protected memory location is not within the set of data values.

7. The apparatus according to claim 6 wherein one of the set of lock values is a floating point not-a-number.