Input/output execution apparatus for a plural-OS run system

• US 5,499,379 A
• Filed: 01/25/1993
• Issued: 03/12/1996
• Est. Priority Date: 06/30/1988
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Sato, Hiroaki, Haraguchi, Masatoshi, Tanaka, Shunji, Sawamoto, Hideo, Yamagata, Ryo, Umeno, Hidenori, Ohtsuki, Toru, Watanabe, Masaya
• Primary Examiner(s): Bowler, Alyssa H.
• Assistant Examiner(s): HARRITY, JOHN E
• Application Number:
  US08/008,842
• Time in Patent Office: 1,142 Days
• Field of Search: 395/700, 395/275, 364/941, 364/976.3, 364/DIG. 2
• US Class Current: 710/40
• CPC Class Codes: G06F 2009/45579 I/O management, e.g. providing access to device drivers or storage
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

A plural-OS run system in which a plurality of operating systems (OSs) capable of operating on machines of different architectures, respectively, are allowed to run on one bare machine under the control of one control program (CP) or one control means. The input/output instruction and input/output interrupt of the operating system capable of running on a machine of the same architecture as that of the bare machine are directly executed on the bare machine without need for translation of the format. The input/output instruction and the input/output interrupt of the operating system adapted to run on a machine of the architecture differing from that of the bare machine are allowed to be directly executed while translating the format.

Claims

1. A computer system for running plural operating systems under control of a control program, said computer system comprising:

(a) a plurality of I/O devices;

(b) a main storage partitioned to said operating systems;

(c) an I/O processor, responsive to an I/O operation request by one of said operating systems which designates a subchannel number assigned to one of the I/O devices and a control signal required for execution of an I/O operation, for executing the I/O operation between said one I/O device and said main storage assigned to said one operating system;

(d) an instruction processor, responsive to an I/O instruction of a first kind issued from a first one of the operating systems which designates a subchannel number and an operand of a first kind which designates an I/O operation to be executed, for providing, without interrupting the control program, said I/O processor with the subchannel number and a control signal designated by the operand of the first kind, said instruction processor comprising;

(e) judging means, responsive to an I/O instruction of a second kind which includes a device address assigned to a second one of the I/O devices and an operand of a second kind which designates an I/O operation to be executed, for judging whether said I/O instruction is issued by a second one of the operating systems, and

(f) I/O instruction execution means, responsive to an affirmative judging by said judging means, for providing said I/O processor with (i) a subchannel number assigned to said second one of the I/O devices and (ii) a control signal corresponding to the operand of the second kind;

interruption subclass indicating means for indicating one or more interruption subclasses for direct input/output execution at the time when an operating system starts to run on an instruction processor; and

TPI (test pending interruption) instruction executing means, wherein;

when the operating system running on said instruction processor issues a TPI (test pending interruption) instruction for releasing an interrupt assigned with a highest priority from interrupts for said one of the input/output devices, when allowability of the interrupt for said input/output device is indicated by an interruption subclass mask, and storing identification information of the input/output device having the interrupt released from suspension in a main storage at a region designated by the TPI instruction,

said TPI instruction execution means responds to the issuance of said TPI instruction to thereby release a pending interrupt having the highest priority assigned thereto from the interrupts for the input/output device of said input/output devices, the interrupt allowability of said input/output device being indicated by said operating system, and store the identification information of the input/output device having the interrupt released in the main storage of said operating system at a region designated by said TPI instruction.

2. A computer system according to claim 1, further including:

interrupt suspension indicating means for indicating whether or not said control program suspends an input/output interrupt of the operating system; and

TPI instruction intercept means for responding to the issuance of the TPI instruction by the operating system running on said instruction processor to thereby intercept said TPI instruction to simulate said TPI instruction by said control program, when said interrupt suspension indicating means indicates a suspension of the intercept.

3. A computer system for running plural operating systems under control of a control program, said computer system comprising:

(a) a plurality of I/O devices;

(b) a main storage partitioned to said operating systems;

(c) an I/O processor, responsive to an I/O operation request by one of said operating systems which designates a subchannel number assigned to one of the I/O devices and a control signal required for execution of an I/O operation, for executing the I/O operation between said one I/O device and said main storage assigned to said one operating system;

(d) an instruction processor, responsive to an I/O instruction of a first kind issued from a first one of the operating systems which designates a subchannel number and an operand of a first kind which designates an I/O operation to be executed, for providing, without interrupting the control program, said I/O processor with the subchannel number and a control signal designated by the operand of the first kind, said instruction processor comprising;

(e) judging means, responsive to an I/O instruction of a second kind which includes a device address assigned to a second one of the I/O devices and an operand of a second kind which designates an I/O operation to be executed, for judging whether said I/O instruction is issued by a second one of the operating systems, and

(f) I/O instruction execution means, responsive to an affirmative judging by said judging means, for providing said I/O processor with (i) a subchannel number assigned to said second one of the I/O devices and (ii) a control signal corresponding to the operand of the second kind; and

TSCH instruction execution means wherein;

when one of the operating systems running on said instruction processor issues to said one of the input/output devices a TSCH (test subchannel) instruction for releasing the input/output device of said input/output devices designated by said TSCH instruction from an interrupt suspension state and storing a state of said input/output device in a main storage at a region designated by said TSCH instruction,

said TSCH instruction execution means responds to the issuance of said TSCH instruction by the operating system to one of the input/output devices dedicated to said operating system for thereby releasing the dedicated input/output device designated by said TSCH instruction from an interrupt suspension state and storing a state of said input/output device in the main storage of said operating system at a region designated by said TSCH instruction.