Method of manufacturing semiconductor device
First Claim
1. A method of manufacturing a CMOS transistor with a n-MOSFET and a p-MOSFET on a semiconductor substrate, comprising the steps of:
- introducing an impurity for controlling threshold value into at least a part to be a channel region of the n-MOSFET of the semiconductor substrate;
introducing an impurity for controlling threshold value into at least a part to be a channel region of the p-MOSFET of the semiconductor substrate;
forming a gate electrode of the n-MOSFET and a gate electrode of the p-MOSFET on the semiconductor substrate;
conducting low-dose ion implant of a p-type impurity to both of the n-MOSFET and the p-MOSFET, using the gate electrodes of the n-MOSFET and the p-MOSFET as masks to form p- regions;
conducting low-dose ion implant of a n-type impurity to both of the n-MOSFET and the p-MOSFET, using the gate electrodes of the n-MOSFET and the p-MOSFET as masks to form n- regions;
forming source/drain regions at the n-MOSFET by heavily introducing a n-type impurity after the steps of low-dose ion implant of the p-type and n-type impurities; and
forming source/drain regions at the p-MOSFET by heavily introducing a p-type impurity after the steps of low-dose ion implant of the p-type and n-type impurities,wherein p- regions to be local punch through stoppers are formed between the source/drain regions and the channel region of the n-MOSFET, and n- regions to be local punch through stoppers are formed between the source/drain regions and the channel regions of the p-MOSFET.
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Abstract
In a CMOS semiconductor device, low-dose ion implant of p-type impurity and n-type impurity is successively conducted to both n-MOSFET and p-MOSFET after formation of gate electrodes. Thereafter, when source/drain regions are formed at each MOSFET, p- regions function as local punch through stoppers in the n-MOSFET and n- regions function as the local punch through stoppers in the p-MOSFET. At this time, respective doses of n-type and p-type impurities are adjusted so that lowerings of threshold values of the channel regions are almost equal to each other. Thus, short channel effect is prevented, while reducing the step of forming two resist masks. With side walls, the CMOS semiconductor device with less short channel effect and high durability to hot carrier is manufactured without increase in the step of forming the resist masks.
43 Citations
9 Claims
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1. A method of manufacturing a CMOS transistor with a n-MOSFET and a p-MOSFET on a semiconductor substrate, comprising the steps of:
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introducing an impurity for controlling threshold value into at least a part to be a channel region of the n-MOSFET of the semiconductor substrate; introducing an impurity for controlling threshold value into at least a part to be a channel region of the p-MOSFET of the semiconductor substrate; forming a gate electrode of the n-MOSFET and a gate electrode of the p-MOSFET on the semiconductor substrate; conducting low-dose ion implant of a p-type impurity to both of the n-MOSFET and the p-MOSFET, using the gate electrodes of the n-MOSFET and the p-MOSFET as masks to form p- regions; conducting low-dose ion implant of a n-type impurity to both of the n-MOSFET and the p-MOSFET, using the gate electrodes of the n-MOSFET and the p-MOSFET as masks to form n- regions; forming source/drain regions at the n-MOSFET by heavily introducing a n-type impurity after the steps of low-dose ion implant of the p-type and n-type impurities; and forming source/drain regions at the p-MOSFET by heavily introducing a p-type impurity after the steps of low-dose ion implant of the p-type and n-type impurities, wherein p- regions to be local punch through stoppers are formed between the source/drain regions and the channel region of the n-MOSFET, and n- regions to be local punch through stoppers are formed between the source/drain regions and the channel regions of the p-MOSFET. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification