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Method of manufacturing semiconductor device

  • US 5,500,379 A
  • Filed: 06/24/1994
  • Issued: 03/19/1996
  • Est. Priority Date: 06/25/1993
  • Status: Expired due to Fees
First Claim
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1. A method of manufacturing a CMOS transistor with a n-MOSFET and a p-MOSFET on a semiconductor substrate, comprising the steps of:

  • introducing an impurity for controlling threshold value into at least a part to be a channel region of the n-MOSFET of the semiconductor substrate;

    introducing an impurity for controlling threshold value into at least a part to be a channel region of the p-MOSFET of the semiconductor substrate;

    forming a gate electrode of the n-MOSFET and a gate electrode of the p-MOSFET on the semiconductor substrate;

    conducting low-dose ion implant of a p-type impurity to both of the n-MOSFET and the p-MOSFET, using the gate electrodes of the n-MOSFET and the p-MOSFET as masks to form p- regions;

    conducting low-dose ion implant of a n-type impurity to both of the n-MOSFET and the p-MOSFET, using the gate electrodes of the n-MOSFET and the p-MOSFET as masks to form n- regions;

    forming source/drain regions at the n-MOSFET by heavily introducing a n-type impurity after the steps of low-dose ion implant of the p-type and n-type impurities; and

    forming source/drain regions at the p-MOSFET by heavily introducing a p-type impurity after the steps of low-dose ion implant of the p-type and n-type impurities,wherein p- regions to be local punch through stoppers are formed between the source/drain regions and the channel region of the n-MOSFET, and n- regions to be local punch through stoppers are formed between the source/drain regions and the channel regions of the p-MOSFET.

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