Differential amplifier circuit with almost linear transconductance

• US 5,500,623 A
• Filed: 12/08/1993
• Issued: 03/19/1996
• Est. Priority Date: 12/08/1992
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Kimura, Katsuji
• Primary Examiner(s): MOTTOLA, STEVEN J
• Application Number:
  US08/162,960
• Time in Patent Office: 832 Days
• Field of Search: 330/252, 330/253, 330/295, 307/494
• US Class Current: 330/252
• CPC Class Codes: H03F 1/3211 in differential amplifiers

Abstract

A differential amplifier circuit having an improved transconductance linearity, which includes a first to fourth unbalanced differential pairs of MOS transistors. In each differential pair, a ratio (W/L) of a gate-width W and a gate-length L of one transistor is different from that of the other transistor. Gates of the transistors having smaller ratios of the first and third pairs and gates of the transistors having larger ratios of the second and fourth pairs are coupled together to form one of differential input ends. Gates of the transistors having larger ratios of the first and third pairs and gates of the transistors having smaller ratios of the second and fourth pairs are coupled together to form the other of the input ends. Drains of the transistors having smaller ratios of the first and second pairs and drains of the transistors having larger ratios of the third and fourth pairs are coupled together to form one of differential output ends. Drains of the transistors having larger ratios of the first and second pairs and drains of the transistors having smaller ratios of the third and fourth pairs are coupled together to form the other of the output ends.

Claims

1. A differential amplifier circuit comprising:

a first differential pair formed of first and second transistors, which is driven by a first constant current source;

a ratio (W/L) of a gate-width W and a gate-length L of said second transistor being K₁ times as much as that of said first transistor where K₁ ≠

1;

a second differential pair formed of third and fourth transistors, which is driven by a second constant current source whose current value is equal to that of said first constant current source;

a ratio (W/L) of a gate-width W and a gate-length L of said third transistor being K₂ times as much as that of said fourth transistor where K₂ ≠

1;

gates of said first and third transistors being coupled together and gates of said second and fourth transistors being coupled together;

drains of said first and fourth transistors being coupled together and drains of said second and third transistors being coupled together;

a third differential pair formed of fifth and sixth transistors, which is driven by a third constant current source;

a ratio (W/L) of a gate-width W and a gate-length L of said sixth transistor being K₃ times as much as that of said fifth transistor where K₃ ≠

1;

a fourth differential pair formed of seventh and eighth transistors, which is driven by a fourth constant current source whose current value is equal to that of said third constant current source;

a ratio (W/L) of a gate-width W and a gate-length L of said seventh transistor being K₄ times as much as that of said eighth transistor where K₄ ≠

1;

gates of said fifth and seventh transistors being coupled together and gates of said sixth and eighth transistors being coupled together; and

drains of said fifth and eighth transistors being coupled together and drains of said sixth and seventh transistors being coupled together;

wherein said gates of said first and third transistors and said gates of said fifth and seventh transistors are coupled together to form one of differential input ends, and said gates of said second and fourth transistors and said gates of said sixth and eighth transistors are coupled together to form the other of said differential input ends;

said drains of said first and fourth transistors and said drains of said sixth and seventh transistors are coupled together to form one of differential output ends, and said drains of said second and third transistors and said drains of said fifth and eighth transistors are coupled together to form the other of said differential output ends; and

at least one of said ratios (W/L) of said fifth and eighth transistors is different from at least one of said ratios (W/L) of said first and fourth transistors.

2. A differential amplifier circuit comprising:

a first differential pair formed of first and second transistors, which is driven by a first constant current source;

a ratio (W/L) of a gate-width W and a gate-length L of said second transistor being K₁ times as much as that of said first transistor where K₁ ≠

1;

a second differential pair formed of third and fourth transistors, which is driven by a second constant current source whose current value is equal to that of said first constant current source;

a ratio (W/L) of a gate-width W and a gate-length L of said third transistor being K₂ times as much as that of said fourth transistor where K₂ ≠

1;

gates of said first and third transistors being coupled together and gates of said second and fourth transistors being coupled together;

drains of said first and fourth transistors being coupled together and drains of said second and third transistors being coupled together;

a third differential pair formed of fifth and sixth transistors, which is driven by a third constant current source;

a ratio (W/L) of a gate-width W and a gate-length L of said sixth transistor being K₃ times as much as that of said fifth transistor where K₃ ≠

1;

a fourth differential pair formed of seventh and eighth transistors, which is driven by a fourth constant current source whose current value is equal to that of said third constant current source;

a ratio (W/L) of a gate-width W and a gate-length L of said seventh transistor being K₄ times as much as that of said eighth transistor where K₄ ≠

1;

gates of said fifth and seventh transistors being coupled together and gates of said sixth and eighth transistors being coupled together; and

drains of said fifth and eighth transistors being coupled together and drains of said sixth and seventh transistors being coupled together;

wherein said gates of said first and third transistors and said gates of said fifth and seventh transistors are coupled together to form one of differential input ends, and said gates of said second and fourth transistors and said gates of said sixth and eighth transistors are coupled together to form the other of said differential input ends;

said drains of said first and fourth transistors and said drains of said sixth and seventh transistors are coupled together to form one of differential output ends, and said drains of said second and third transistors and said drains of said fifth and eighth transistors are coupled together to form the other of said differential output ends; and

at least one of K₃ and K₄ of said third and fourth differential pairs is different from at least one of K₁ and K₂ of said first and second differential pairs.

3. A differential amplifier circuit comprising:

a first differential pair formed of first and second transistors, which is driven by a first constant current source;

a ratio (W/L) of a gate-width W and a gate-length L of said second transistor being K₁ times as much as that of said first transistor where K₁ ≠

1;

a second differential pair formed of third and fourth transistors, which is driven by a second constant current source whose current value is equal to that of said first constant current source;

a ratio (W/L) of a gate-width W and a gate-length L of said third transistor being K₂ times as much as that of said fourth transistor where K₂ ≠

1;

gates of said first and third transistors being coupled together and gates of said second and fourth transistors being coupled together;

drains of said first and fourth transistors being coupled together and drains of said second and third transistors being coupled together;

a third differential pair formed of fifth and sixth transistors, which is driven by a third constant current source;

a ratio (W/L) of a gate-width W and a gate-length L of said sixth transistor being K₃ times as much as that of said fifth transistor where K₃ ≠

1;

a fourth differential pair formed of seventh and eighth transistors, which is driven by a fourth constant current source whose current value is equal to that of said third constant current source;

a ratio (W/L) of a gate-width W and a gate-length L of said seventh transistor being K₄ times as much as that of said eighth transistor where K₄ ≠

1;

gates of said fifth and seventh transistors being coupled together and gates of said sixth and eighth transistors being coupled together; and

drains of said fifth and eighth transistors being coupled together and drains of said sixth and seventh transistors being coupled together;

wherein said gates of said first and third transistors and said gates of said fifth and seventh transistors are coupled together to form one of differential input ends, and said gates of said second and fourth transistors and said gates of said sixth and eighth transistors are coupled together to form the other of said differential input ends;

said drains of said first and fourth transistors and said drains of said sixth and seventh transistors are coupled together to form one of differential output ends, and said drains of said second and third transistors and said drains of said fifth and eighth transistors are coupled together to form the other of said differential output ends; and

said current values of said first and second constant current sources are different from those of said third and fourth constant current sources.

4. A differential amplifier circuit comprising:

a first differential pair formed of first and second transistors, which is driven by a first constant current source;

a ratio (W/L) of a gate-width W and a gate-length L of said second transistor being K times as much as that of said first transistor where K≠

1;

a second differential pair formed of third and fourth transistors, which is driven by a second constant current source whose current value is equal to that of said first constant current source;

a ratio (W/L) of a gate-width W and a gate-length L of said third transistor being K times as much as that of said fourth transistor;

gates of said first and third transistors being coupled together and gates of said second and fourth transistors being coupled together;

drains of said first and fourth transistors being coupled together and drains of said second and third transistors being coupled together;

a third differential pair formed of fifth and sixth transistors, which is driven by a third constant current source;

a ratio (W/L) of a gate-width W and a gate-length L of said fifth transistor being b times as much as that of said first transistor where b≠

1, and a ratio (W/L) of a gate-width W and a gate-length L of said sixth transistor being K'"'"'b times as much as that of said first transistor where K'"'"'≠

1;

a fourth differential pair formed of seventh and eighth transistors, which is driven by a fourth constant current source whose current value is equal to that of said third constant current source;

a ratio (W/L) of a gate-width W and a gate-length L of said seventh transistor being K'"'"'b times as much as that of said first transistor, and a ratio (W/L) of a gate-width W and a gate-length L of said eighth transistor being b times as much as that of said first transistor;

gates of said fifth and seventh transistors being coupled together and gates of said sixth and eighth transistors being coupled together; and

drains of said fifth and eighth transistors being coupled together and drains of said sixth and seventh transistors being coupled together;

wherein said gates of said first and third transistors and said gates of said fifth and seventh transistors are coupled together to form one of differential input ends, and said gates of said second and fourth transistors and said gates of said sixth and eighth transistors are coupled together to form the other of said differential input ends;

said drains of said first and fourth transistors and said drains of said sixth and seventh transistors are coupled together to form one of differential output ends, and said drains of said second and third transistors and said drains of said fifth and eighth transistors are coupled together to form the other of said differential output ends; and

said current values of said third and fourth constant current sources are a times as much as those of said first and second constant current sources where a≠

1.

5. A differential amplifier circuit comprising:

a first differential pair formed of first and second transistors, which is driven by a first constant current source;

a ratio (W/L) of a gate-width W and a gate-length L of said second transistor being equal to that of said first transistor;

a second differential pair formed of third and fourth transistors, which is driven by a second constant current source whose current value is equal to that of said first constant current source;

a ratio (W/L) of a gate-width W and a gate-length L of said fourth transistor being equal to that of said third transistor;

a third differential pair formed of fifth and sixth transistors, which is driven by a third constant current source whose current value is different from those of said first and second constant current sources;

a ratio (W/L) of a gate-width W and a gate-length L of said sixth transistor being equal to that of said fifth transistor;

said ratio (W/L) of said fifth and sixth transistors being different from those of said first, second, third and fourth transistors;

gates of said first and third transistors being coupled together and gates of said second and fourth transistors being coupled together to form differential input ends; and

drains of said first, third and sixth transistors being coupled together and drains of said second, fourth and fifth transistors being coupled together to form differential output ends;

wherein a first DC voltage is applied across said gates of said first and third transistors and a second DC voltage is applied across said gates of said second and fourth transistors; and

a polarity of said first DC voltage with respect to said gate of said first transistor is the same as that of said second DC voltage with respect to said gate of said fourth transistor.

6. A differential amplifier circuit as claimed in claim 5, wherein said ratios (W/L) of said first, second, third and fourth transistors are equal to each other, and values of said first and second DC voltages are equal to each other.

7. A differential amplifier circuit comprising:

a first differential pair formed of first and second transistors, which is driven by a first constant current source;

a ratio (W/L) of a gate-width W and a gate-length L of said second transistor being K times as much as that of said first transistor where K≠

1;

a second differential pair formed of third and fourth transistors, which is driven by a second constant current source whose current value is equal to that of said first constant current source;

a ratio (W/L) of a gate-width W and a gate-length L of said fourth transistor being K times as much as that of said third transistor;

gates of said first and fourth transistors being coupled together to form one of differential input ends and gates of said second and third transistors being coupled together to form the other of said differential input ends; and

drains of said first and third transistors being coupled together to form one of differential output ends and drains of said second and fourth transistors being coupled together to form the other of said differential output ends;

wherein said ratio K is 9.5.

8. A differential amplifier circuit as claimed in claim 7, wherein said gate-lengths L of said first and third transistors are equal to each other.

9. A differential amplifier circuit comprising:

a first differential pair formed of first and second transistors, which is driven by a first constant current source;

a second differential pair formed of third and fourth transistors, which is driven by a second constant current source whose current value is equal to that of said first constant current source;

a third differential pair formed of fifth and sixth transistors, which is driven by a third constant current source whose current value is different from those of said first and second constant current sources;

bases of said first and fifth transistors being coupled together and bases of said fourth and sixth transistors being coupled together to form differential input ends; and

collectors of said first, third and fifth transistors being coupled together and drains of said second, fourth and sixth transistors being coupled together to form differential output ends;

wherein a first DC voltage is applied across said bases of said first and third transistors and a second DC voltage is applied across said bases of said second and fourth transistors; and

a polarity of said first DC voltage with respect to said base of said first transistor is the same as that of said second DC voltage with respect to said base of said fourth transistor.

10. A differential amplifier circuit as claimed in claim 9,

wherein values of said first and second DC voltages are both 2.634 V_T, where V_T is the thermal voltage defined as V_T =(k_B T/q) where K_B is Boltzmann'"'"'s constant, T is absolute temperature and q is the charge of an electron;

and

values of said first and second constant current sources are both (4/3) times as much as that of said third constant current sources.

11. A differential amplifier circuit as claimed in claim 9,

wherein values of said first and second DC voltages are both 2.06344 V_T, where V_T is the thermal voltage defined as V_T =(k_B T/q) where K_B is Boltzmann'"'"'s constant, T is absolute temperature and q is the charge of an electron;

and

values of said first and second constant current sources are both 1.5625 times as much as that of said third constant current source.

12. A differential amplifier circuit comprising:

a first differential pair formed of first and second transistors, which is driven by a first constant current source;

a second differential pair formed of third and fourth transistors, which is driven by a second constant current source whose current value is equal to that of said first constant current source;

a third differential pair formed of fifth and sixth transistors, which is driven by a third constant current source whose current value is different from those of said first and second constant current sources;

a fourth differential pair formed of seventh and eighth transistors, which is driven by a fourth constant current source whose current value is different from those of said first and second constant current sources;

bases of said first and fifth transistors being coupled together and bases of said fourth and eighth transistors being coupled together to form differential input ends; and

collectors of said first, third, fifth and seventh transistors being coupled together and collectors of said second, fourth, sixth and eighth transistors being coupled together to form differential output ends;

wherein a first DC voltage is applied across said bases of said first and third transistors, a second DC voltage is applied across said bases of said second and fourth transistors, a third DC voltage is applied across said bases of said fifth and seventh transistors, and a fourth DC voltage is applied across said bases of said sixth and eighth transistors; and

a polarity of said first DC voltage with respect to said base of said first transistor is the same as that of said second DC voltage with respect to said base of said fourth transistor, and a polarity of said third DC voltage with respect to said base of said fifth transistor is the same as that of said fourth DC voltage with respect to said base of said eighth transistor.

13. A differential amplifier circuit as claimed in claim 12, wherein values of said first and second DC voltages are both 1.2 V_T and those of said third and fourth DC voltages are both 3.834 V_T, where V_T is the thermal voltage defined as V_T =(k_B T/q) where K_B is Boltzmann'"'"'s constant, T is absolute temperature and q is the charge of an electron;

and

values of said third and fourth constant current sources are both 1.3 times as much as those of said first and second constant current sources.

14. A differential amplifier circuit as claimed in claim 12,

wherein values of said first and second DC voltages are both 0.70814 V_T and those of said third and fourth DC voltages are both 2.59546 V_T, where V_T is the thermal voltage defined as V_T =(k_B T/q) where K_B is Boltzmann'"'"'s constant, T is absolute temperature and q is the charge of an electron;

and

values of said third and fourth constant current sources are both 1.82532 times as much as those of said first and second constant current sources.