Vehicular goodwill message system

• US 5,500,638 A
• Filed: 01/26/1994
• Issued: 03/19/1996
• Est. Priority Date: 01/26/1994
• Status: Expired due to Fees

• Current Assignee: Ikoma A.V. George
• Original Assignee: Ikoma A.V. George
• Inventors: George, Ikoma A. V.
• Primary Examiner(s): Peng, John K.
• Assistant Examiner(s): Lefkowitz, Edward
• Application Number:
  US08/186,433
• Time in Patent Office: 783 Days
• Field of Search: 340/468, 340/471, 340/472, 340/479, 40/591, 362/61, 362/80.1
• US Class Current: 340/468
• CPC Class Codes: B60Q 1/50 for indicating other intentions or conditions, e.g. request for waiting or overtaking
• CPC Class Codes: B60Q 1/5035 electronic displays
• CPC Class Codes: B60Q 1/52 for indicating emergencies
• CPC Class Codes: B60Q 1/549 for expressing greetings, gratitude or emotions

Abstract

A method of communication between vehicle operators. The invention employs common display LEDs, the segments of which when appropriately turned on issue desired messages on the reader board for the operators of other vehicles. To issue a message the operator of a vehicle simply depresses a button on the control box, the operator of a vehicle behind sees the message for a length of time set by a monostable timmer.

Claims

1. A vehicular goodwill message system for displaying messages comprising:

(a) a logic circuit comprising a plurality of logic gates for receiving at least four timed signals and for supplying at least seven output signals and for electrically communicating with a timing means and a display means;

(b) a control means (30) for regulating at least four switch lines in electrical communication with a timing means comprising a control box for supporting at least four switch members;

said control means additionally comprising a first switch member (S), a second switch member (Y), a third switch member (H), and a fourth switch member (P);

(c) a timing means for receiving said least four switch lines and communicating with said least four switch lines and for providing at least four timed signals therefrom corresponding to said least four switch lines and for establishing an energizing interval for said least four timed signals and for electrically communicating with said logic circuit and said control means;

(d) a display means consisting of a plurality of light emitting diodes for receiving said least seven output signals and said least four timed signals responsive to and in communication with said least four timed signals of said timing means and said least seven output signals of said logic circuit such that said display means is caused to operate when one of said least four timed signals is energized and at least one of said least seven output signals is energized for displaying messages; and

(e) a housing for supporting said logic circuit, said timing means, and said display means, and comprising a translucent front panel member wherethrough the displayed messages are visable.

2. The apparatus of claim 1 wherein said control means additionally comprises a power supply line;

said least four switch lines comprising a first switch line (9), a second switch line (8), a third switch line (7), and a fourth switch line (6);

said first switch member (S) communicating with said power supply line and said first switch line (9) to switchably complete a first circuit between said power supply line and said first switch line;

said second switch member (Y) communicating with said power supply line and said second switch line (8) to switchably complete a second circuit between said power supply line and said second switch line;

said third switch member (H) communicating with said power supply line and said third switch line (7) to switchably complete a third circuit between said power supply line and said third switch line; and

said fourth switch member (P) communicating with said power supply line and said fourth switch line (6) to switchably complete a fourth circuit between said power supply line and said fourth switch line.

3. The apparatus of claim 2 additionally comprising a voltage changing means (50) for operatively changing an operating voltage level of said first switch line (9), said second switch line (8), said third switch line (7), and said fourth switch line (6);

said operating voltage being about 5 volts; and

an operating voltage power supply line (1) in communication with said timing means.

4. The apparatus of claim 3 wherein said timing means comprises means for receiving said first switch line (9), said second switch line (8), said third switch line (7), said fourth switch line (6), and said operating voltage power supply line (1), and for providing and energizing said least four timed lines such that when said first switch line (9) is energized a first timed line (12) is accordingly activated, when said second switch line (8) is energized a second timed line (13) is accordingly activated, when said third switch line (7) is energized a third timed line (14) is accordingly activated, and when said fourth switch line (6) is energized a fourth timed line (15) is accordingly activated.

5. The apparatus of claim 4 wherein said logic circuit comprises a first OR gate (105) interconnected to said first timed line (12), said second timed line (13), said third timed line (14), said fourth timed line (15), and having a first output line (16);

a second OR gate (110) interconnected to said third timed line (14) and said fourth timed line (15) and having a second output line (21);

a third OR gate (115) interconnected to said first timed line (12), said third timed line (14), and said fourth timed line (15), and having a third output line (17);

a fourth OR gate (120) interconnected to said first timed line (12) and said third timed line (14) and having a fourth output line (18);

a fifth OR gate (125) interconnected to said first timed line (12) and to said fourth timed line (15) and having a fifth output line (19);

a sixth OR gate (130) interconnected to said second timed line (13), said third timed line (14), and said fourth timed line (15), and having a sixth output line (22); and

a seventh OR gate (135) interconnected to said first timed line (12) and to said second timed line (13) and having a seventh output line (20) .

6. The apparatus of claim 5 wherein said display means comprises a plurality of seven-segment light emitting diode assemblies interconnected with said least seven output signals of said logic circuit and said least four timed circuit lines.

7. The apparatus of claim 5 wherein said display means comprises a first LED assembly interconnected with said second output line and comprising a seven-segment LED assembly;

a second LED assembly interconnected with said second output line and comprising a seven-segment LED assembly;

a third LED assembly interconnected with said second output line and said third output line and comprising a seven-segment LED assembly;

a fourth LED assembly interconnected with said second timed line, said first output line, said second output line, said third output line, and said sixth output line and comprising a seven-segment LED assembly;

a fifth LED assembly interconnected with said first timed line, said third output line, said sixth output line, and said seventh output line and comprising a seven-segment LED assembly;

a sixth LED assembly interconnected with said first timed line, said first output line, said second output line, and said third output line and comprising a seven-segment LED assembly;

a seventh LED assembly interconnected with said first timed line, said second timed line, and said third output line and comprising a fourteen-segment LED assembly;

an eighth LED assembly interconnected with said first timed line, said second timed line, and said third output line and comprising a fourteen-segment LED assembly;

a ninth LED assembly interconnected with said second output line, said third output line, said fourth output line, and said fifth output line and comprising a seven-segment LED assembly;

a tenth LED assembly interconnected with said second output line, said third output line, said fourth output line, and said fifth output line and comprising a seven-segment LED assembly;

an eleventh LED assembly interconnected with said first timed line and said third output line and comprising a seven-segment LED assembly;

a twelfth LED assembly interconnected with said third timed line, said fourth timed line, and said second output line and comprising a seven-segment LED assembly;

a thirteenth LED assembly interconnected with said fourth timed line and comprising a seven-segment LED assembly;

a fourteenth LED assembly interconnected with said fourth timed line and comprising a seven-segment LED assembly; and

a fifteenth LED assembly interconnected with said fourth timed line and comprising a seven-segment LED assembly.

8. The apparatus of claim 4 wherein said timing means further comprises a first monostable timing I.C. (55) interconnected with said first switch line (9), said second switch line (8) and said operating voltage power supply line (1), and producing a first timed voltage interval along said first timed line (12) and said second timed line (13);

a second monostable timing I.C. (60) interconnected with said third switch line (7), said fourth switch line (8), and said operating voltage power supply line (1), and producing a second timed voltage interval along a first intermediate line (10) and a second intermediate line (11), and producing a second timed voltage interval along said first intermediate line (10) and said second intermediate line (11); and

an astable timing I.C. (65) interconnected with said first intermediate line (10), said second intermediate line (11), and said operating voltage power supply line (1), and producing a third timed voltage interval along said third timed line (14) and said fourth timed line (15).

9. The apparatus of claim 8 wherein said seventh LED assembly (170) comprises a fourteen-segment LED assembly and wherein said eighth LED assembly (175) comprises a fourteen-segment LED assembly.