Device for encoding digital signals representing images, and corresponding decoding device

• US 5,500,677 A
• Filed: 06/07/1995
• Issued: 03/19/1996
• Est. Priority Date: 10/28/1992
• Status: Expired due to Term

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Fert, Etienne
• Primary Examiner(s): Chin, Tommy P.
• Assistant Examiner(s): RAO, ANAND SHASHIKANT
• Application Number:
  US08/483,916
• Time in Patent Office: 286 Days
• Field of Search: 348/413, 348/416, 348/419, 348/405, 348/699, 348/402, 348/700, 348/462
• US Class Current: 375/240.12
• CPC Class Codes: H04N 19/124 Quantisation
• CPC Class Codes: H04N 19/146 Data rate or code amount at the encoder output
• CPC Class Codes: H04N 19/152 by measuring the fullness of the transmission buffer
• CPC Class Codes: H04N 19/176 the region being a block, e.g. a macroblock
• CPC Class Codes: H04N 19/187 the unit being a scalable video layer
• CPC Class Codes: H04N 19/30 using hierarchical techniques, e.g. scalability H04N19/63 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

A device for encoding digital signals corresponding to images which are subdivided into blocks has a first encoding channel including a discrete cosine transform circuit. In addition to this first encoding channel the device has a second encoding channel which encodes the differences between the original coefficients present at the output of the discrete cosine transform circuit and the same coefficients after quantization and inverse quantization. This second channel encodes the differences after they are quantized with a finer quantization step than in the first encoding channel. The device further includes a prediction channel including a motion compensation stage, that uses both the inverse quantized coefficients coded in the first encoding channel and the inverse quantized coefficients coded in the second encoding channel to produce a predicted digital signal. This predicted digital signal is subtracted from the digital signal to be encoded by the device.

Claims

1. An encoding device for encoding a digital signal corresponding to images subdivided into blocks, comprising:

a discrete cosine transform circuit for processing a first digital signal to obtain first coefficients;

a first quantizing circuit for quantizing the first coefficients to obtain first quantized values, said first quantizing circuit having a first quantization step;

a first encoding circuit for encoding the first quantized values to obtain first encoded signals having a first quality level;

a first inverse quantization circuit for dequantizing the first quantized values to obtain first dequantized coefficients;

a first subtracter for subtracting the first dequantized coefficients from the first coefficients to obtain second coefficients;

a second quantizing circuit provided in cascade with the first quantizing circuit for quantizing the second coefficients to obtain second quantized values, said second quantizing circuit having a second quantization step which is finer than the first quantization step;

a second encoding circuit for encoding the second quantized values to obtain second encoded signals having a second quality level, which is higher than the first quality level;

a second inverse quantization circuit for dequantizing the second quantized values to obtain second dequantized coefficients;

a first adder circuit for adding the first dequantized coefficients and the second dequantized coefficients to obtain third coefficients;

an inverse discrete cosine transform circuit for processing the third coefficients to obtain a third digital signal;

a second adder circuit for adding the third digital signal and a predicted digital signal to obtain a fourth digital signal;

a picture memory for storing and supplying the fourth digital signal;

a motion compensation stage for operating on the fourth digital signal to produce the predicted digital signal; and

a second subtracter circuit for subtracting the predicted digital signal from the digital signal to obtain the first digital signal.

2. A encoding device as claimed in claim 1, further comprising:

a first buffer memory for storing and supplying the first encoded signals;

a first rate control circuit for supplying the first quantization step to the first quantizing circuit;

a second buffer memory for storing and supplying the second encoded signals; and

a second rate control circuit for supplying the second quantization step to the second quantizing circuit,

3. A decoding device for decoding signals previously encoded by means of an encoding device as claimed in claim 1, comprising:

a first decoding circuit for decoding a reproduction of the first encoded signals to obtain first decoder quantized values;

a first decoder inverse quantization circuit for dequantizing in accordance with the first quantization step the first decoder quantized values to obtain first decoder dequantized coefficients;

a second decoding circuit for decoding a reproduction of the second encoded signals to obtain second decoder quantized values;

a second decoder inverse quantization circuit for dequantizing in accordance with the second quantization step the second decoder quantized values to obtain second decoder dequantized coefficients;

a first decoder adder circuit for adding the first decoder dequantized coefficients and the second decoder dequantized coefficients to obtain third decoder quantized coefficients;

a decoder inverse discrete cosine transform circuit for processing the third coefficients to obtain a first decoder digital signal;

a second decoder adder circuit for adding the first decoder digital signal and a second decoder digital signal to obtain a third decoder digital signal;

a picture memory for storing and supplying the third decoder digital signal; and

a motion compensation stage for operating on the third decoder digital signal to obtain the second decoder digital signal;

4. A decoding device as claimed in claim 3 comprising:

a switch arranged between said second decoder inverse quantization circuit and said first decoder adder circuit for rendering an influence of the second decoder dequantized coefficients on the third coefficients inoperative.