Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit

• US 5,502,333 A
• Filed: 03/30/1994
• Issued: 03/26/1996
• Est. Priority Date: 03/30/1994
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Bertin, Claude L., Hedberg, Erik L., Howell, Wayne J.
• Primary Examiner(s): Mintel, William
• Assistant Examiner(s): POTTER, ROY KARL
• Application Number:
  US08/220,086
• Time in Patent Office: 727 Days
• Field of Search: 257/690, 257/691, 257/694, 257/773, 257/777, 257/723, 257/685, 257/686, 365/200
• US Class Current: 257/685
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48235 connecting the wire to a via metallisation of the item
• CPC Class Codes: H01L 2224/4911 the connectors being bonded to at least one common bonding area, e.g. daisy chain
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing
• CPC Class Codes: H01L 23/5382 Adaptable interconnections, e.g. for engineering changes
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01058 : Cerium [Ce]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19107 : off-chip wires

Abstract

Electronic semiconductor structures utilize an electrically programmable spare circuit incorporated with a multichip package. The programmable sparing capability in the multichip package is accomplished either with or without the inclusion of a spare chip(s). With a spare memory circuit, individual failed memory cells in the semiconductor chips of a stack can be functionally replaced by memory cells of the spare memory circuit subsequent to encapsulation and burn-in testing. With use of a spare chip, non-volatile sparing can occur subsequent to encapsulation and burn-in testing without physical rewiring of a wire bond connection. Specific details of alternate electronic semiconductor structures, and fabrication and sparing methods therefore, are set forth.

Claims

1. An electronic semiconductor structure comprising:

a plurality of semiconductor chips electrically coupled together in a system, at least one semiconductor chip of the plurality of semiconductor chips having a memory with m memory cells, wherein m is an integer;

a control circuit for coupling said plurality of semiconductor chips to external circuitry, said control circuit including selection means for facilitating access to a selected semiconductor chip, said selected semiconductor chip comprising one semiconductor chip of the at least one semiconductor chip having a memory, said selected semiconductor chip corresponding to an address received from the external circuitry, said control circuit including a plurality of circuit paths;

a spare memory circuit functionally integrated with said plurality of circuit paths of said control circuit, and having n memory cells, wherein n is an integer and n≦

m, said spare memory circuit being electrically connected to said at least one semiconductor chip having said memory and being programmable such that a single memory cell of the n memory cells of the spare memory circuit can functionally replace a single failed memory cell of said m memory cells of the at least one semiconductor chip having said memory.

2. The electronic semiconductor structure of claim 1, wherein each semiconductor chip of said plurality of semiconductor chips comprises a semiconductor memory chip having said memory with m memory cells.

3. The electronic semiconductor structure of claim 2, wherein said semiconductor memory chips are mechanically coupled together as a multichip stack.

4. The electronic semiconductor structure of claim 3, wherein said spare memory circuit is programmable to account for multiple memory cell failures in the multichip stack by functionally replacing each failed memory cell with a memory cell of the n memory cells of the spare memory circuit.

5. The electronic semiconductor structure of claim 1, wherein said plurality of semiconductor chips comprises a plurality of DRAM chips.

6. The electronic semiconductor structure of claim 5, wherein said spare memory circuit comprises a SRAM circuit, said plurality of DRAM chips and said SRAM circuit being mechanically coupled together in said system.

7. The electronic semiconductor structure of claim 1, wherein said spare memory circuit is programmable such that a plurality of memory cells of the n memory cells can functionally replace a corresponding plurality of failed memory cells of the at least one semiconductor chip having said memory with m memory cells.

8. The electronic semiconductor structure of claim 1, wherein said spare memory circuit is integrated with said control circuit as an integrated circuit.

9. The electronic semiconductor structure of claim 8, wherein said plurality of semiconductor chips comprises a plurality of semiconductor memory chips, each semiconductor memory chip having said memory with m memory cells, said plurality of semiconductor memory chips being mechanically coupled together as a multichip stack, and wherein said integrated circuit resides on a separate logic/memory chip mechanically and electrically coupled to said multichip stack.

10. The electronic semiconductor structure of claim 1, wherein said plurality of semiconductor chips comprises a plurality of semiconductor memory chips, each semiconductor memory chip having said memory with m memory cells, said semiconductor memory chips being mechanically coupled together as a multichip stack, and wherein said spare memory circuit and said control circuit reside on a separate semiconductor chip mechanically and electrically coupled to said multichip stack.

11. The electronic semiconductor structure of claim 10, wherein said multichip stack includes an end surface and at least one side surface, and wherein said separate semiconductor chip is mechanically affixed to said multichip stack at either said end surface or said at least one side surface.

12. The electronic semiconductor structure of claim 1, wherein each semiconductor chip of said plurality of semiconductor chips comprises a semiconductor memory chip having said memory with m memory cells, said plurality of semiconductor memory chips being mechanically coupled together as a multichip stack, and wherein said electronic semiconductor structure further comprises an endcap mechanically coupled to said plurality of semiconductor memory chips as part of said multichip stack, said spare memory circuit and said control circuit residing on said endcap.

13. The electronic semiconductor structure of claim 1, wherein said plurality of semiconductor chips, said control circuit and said spare memory circuit are mechanically coupled together in a multichip package, and wherein said electronic semiconductor structure further comprises means for electrically programming said spare memory circuit within said multichip package.

14. The electronic semiconductor structure of claim 13, wherein said means for electrically programming includes a programmable control means for retaining an address of the single failed memory cell of said m memory cells of the at least one semiconductor chip having said memory.

15. The electronic semiconductor structure of claim 1, wherein said plurality of semiconductor chips comprise a plurality of DRAM chips, and wherein said control circuit further comprises means for interfacing with said external circuitry using signals of a type for a single DRAM chip.

16. The electronic semiconductor structure of claim 15, wherein said spare memory circuit includes an address input, a RAS input, a CAS input, a RAS comparator coupled to said RAS input and said address input, and a CAS comparator coupled to said CAS input and said address input, and wherein an address presented on said address input is examined in said RAS comparator when said RAS input is engaged and said address is examined in said CAS comparator when said CAS input is engaged such that attempted access to said single failed memory cell is detected.

17. The electronic semiconductor structure of claim 16, wherein said spare memory circuit comprises a RAS failed address store separate from a CAS failed address store, said RAS failed address store being coupled to said RAS comparator and said CAS failed address store being coupled to said CAS comparator.

18. The electronic semiconductor structure of claim 16, wherein said spare memory circuit further comprises a redundant word generator coupled to said RAS comparator and a redundant bit generator coupled to said CAS comparator such that faulty bit replacement and faulty word replacement are both facilitated by said spare memory circuit.

19. The electronic semiconductor structure of claim 15, wherein said control circuit comprises data input buffers for reducing the electrical load presented by the control circuit to said external circuitry to substantially that of a single DRAM chip.

20. The electronic semiconductor structure of claim 15, wherein said control circuit includes means for interfacing using JEDEC DRAM compatible signals to said external circuitry.

21. An electronic semiconductor structure comprising:

a plurality of semiconductor chips electrically and mechanically coupled together in a packaged system;

a sparing circuit electrically coupled to the plurality of semiconductor chips and comprising part of the packaged system;

electrically programmable, non-volatile means for activating the sparing circuit to permanently function in combination with at least one semiconductor chip of the plurality of semiconductor chips in the packaged system;

a control circuit for coupling said plurality of semiconductor chips to external circuitry, said control circuit including selection means for facilitating access to a selected semiconductor chip of the at least one semiconductor chip, said selected semiconductor chip corresponding to an address received from the said external circuitry, said control circuit including a plurality of circuit paths common to, and functionally integrated with, said sparing circuit.

22. The electronic semiconductor structure of claim 21, wherein said sparing circuit comprises a logic circuit, and wherein said electrically programmable, non-volatile electrical means comprises means for activating said logic circuit to permanently operate in combination with the at least one semiconductor chip without physical rewiring of an electrical connection within the packaged system.

23. The electronic semiconductor structure of claim 21, wherein said spare circuit comprises a memory circuit, and wherein said electrically programmable, non-volatile means comprises means for activating said memory circuit to permanently operate in combination with the at least one semiconductor chip without physical rewiring of an electrical connection within the packaged system.

24. The electronic semiconductor structure of claim 23, wherein said memory circuit comprises a volatile memory circuit and wherein said electrically programmable, non-volatile means for activating comprises one of an electrical fuse array, a non-volatile memory, and an electrically programmable logic array.

25. The electronic semiconductor structure of claim 21, wherein said electrically programmable non-volatile means comprises part of the packaged system, and wherein said electronic semiconductor structure further comprises a structure surrounding said plurality of semiconductor chips, said sparing circuit and said electrically programmable non-volatile means.