High voltage integrated circuit driver for half-bridge circuit employing a bootstrap diode emulator

• US 5,502,632 A
• Filed: 07/15/1994
• Issued: 03/26/1996
• Est. Priority Date: 05/07/1993
• Status: Expired due to Fees

• Current Assignee: Philips Electronics North America Corporation (Koninklijke Philips N.V.)
• Original Assignee: Philips Electronics North America Corporation (Koninklijke Philips N.V.)
• Inventors: Warmerdam, Leo F. P., Janaswamy, Anand
• Primary Examiner(s): NGUYEN, MATTHEW VAN
• Application Number:
  US08/275,569
• Time in Patent Office: 620 Days
• Field of Search: 363/16, 363/17, 363/56, 363/97, 363/98, 363/131, 363/132, 327/387, 327/390, 327/423, 327/494
• US Class Current: 363/98
• CPC Class Codes: H02M 7/538 in a push-pull configuration H02M7/5375 takes precedence ; with oscillating arrangements H02M7/53832, H02M7/53846
• CPC Class Codes: H03F 2200/31 the switching power stage comprising circuitry for emulating the behaviour of a bootstrap diode
• CPC Class Codes: H03F 3/2171 with field-effect devices H03F3/2173 - H03F3/2178 take precedence
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor

Abstract

A half-bridge driver circuit including a lower drive module and a floating upper drive module for driving respective external upper and lower power transistors of a high voltage half bridge is contained in an integrated circuit chip which includes an on-chip bootstrap diode emulator for charging an external bootstrap capacitor that powers the upper drive module. The upper drive is accommodated in an insulated well and the diode emulator includes as its main current carrying element, a LDMOS transistor formed along the periphery of the well. The LDMOS transistor is driven into a conducting state at the same time the lower power transistor is driven into a conducting state. A clamp and current source solidly bias the backate of the LDMOS while limiting the current drawn by a parasitic transistor attached to the backgate during startup of the LDMOS.

Claims

1. A circuit for driving a half-bridge formed by lower and upper power transistors connected between an output terminal and respective lower and upper rails of a high voltage DC supply, and for charging a bootstrap capacitor having first and second ends, the first end being connected to said output terminal, said circuit comprising:

means for generating lower and upper drive command signals for commanding driving said respective lower and upper power transistors to non-contemporaneous conducting states;

power supply means for generating at a power supply output a relatively low control voltage with respect to said lower rail;

a lower drive module connected to the power supply output for being powered by said relatively low control voltage and comprising means for applying a lower drive control signal between a control electrode of the lower power transistor and the lower rail in response to said lower drive command signal;

an upper drive module adapted to be connected to the first end of the bootstrap capacitor for being powered by a bootstrap voltage across said bootstrap capacitor and comprising means for applying an upper transistor control signal between a control electrode of the upper power transistor and the output terminal in response to said upper drive input control signal; and

bootstrap diode emulator means for charging said bootstrap capacitor to said bootstrap voltage, said bootstrap diode emulator means comprising a Lateral Diffused Metal Oxide Semiconductor (LDMOS) transistor having a source electrode connected to said power supply output, a drain electrode adapted to be connected to the second end of the bootstrap capacitor, a gate electrode coupled to a further control signal derived from said lower drive command signal for driving said LDMOS transistor to a conducting state when the lower power transistor is driven to a conducting state, and a backgate electrode, there being a parasitic transistor connected to said backgate electrode, and biasing and limiting means coupled to the backgate electrode for biasing the backgate electrode while limiting the current that said parasitic transistor can shunt away from said bootstrap capacitor.

2. A circuit as claimed in claim 1, wherein said biasing and limiting means comprises a clamping transistor and a current source connected to said backgate electrode.

3. A circuit as claimed in claim 2, wherein said current source comprises an output of a current mirror.

4. A circuit as claimed in claim 1, further comprising means for deriving said further control signal from said lower drive command signal, said means for deriving comprising a buffer fed by said lower drive command signal to produce a buffer output signal having a voltage range between said lower rail and said relatively low supply voltage, and means for translating the voltage range of said buffer output signal to a range of voltage difference between a point coupled to said gate electrode and said source electrode.

5. A circuit as claimed in claim 2, further comprising means for deriving said further control signal from said lower drive command signal, said means for deriving comprising a buffer fed by said lower drive command signal to produce a buffer output signal having a voltage range between said lower rail and said relatively low supply voltage, and means for translating the voltage range of said buffer output signal to a range of voltage difference between a point coupled to said gate electrode and said source electrode.

6. A circuit as claimed in claim 3, further comprising means for deriving said further control signal from said lower drive command signal, said means for deriving comprising a buffer fed by said lower drive command signal to produce a buffer output signal having a voltage range between said lower rail and said relatively low supply voltage, and means for translating the voltage range of said buffer output signal to a range of voltage difference between a point coupled to said gate electrode and said source electrode.

7. A circuit as claimed in claim 1, further comprising means for deriving said further control signal from said lower drive command signal, said means for deriving further comprising means for clamping said gate electrode to said source electrode of said LDMOS transistor in response to displacement current flowing in a Miller capacitance of said LDMOS transistor coupled between the drain and gate electrodes.

8. A circuit as claimed in claim 2, further comprising means for deriving said further control signal from said lower drive command signal, said means for deriving further comprising means for clamping said gate electrode to said drain electrode of said LDMOS transistor in response to displacement current flowing in a Miller capacitance of said LDMOS transistor coupled between the gate and drain electrodes.

9. A circuit as claimed in claim 3, further comprising means for deriving said further control signal from said lower drive command signal, said means for deriving further comprising means for clamping said gate electrode to said source electrode of said LDMOS transistor in response to displacement current flowing in a Miller capacitance of said LDMOS transistor coupled between the drain and gate electrodes.

10. A circuit as claimed in claim 4, wherein said means for deriving said further control signal from said lower drive command signal further comprises means for clamping said gate electrode to said source electrode of said LDMOS transistor in response to displacement current flowing in a Miller capacitance of said LDMOS transistor coupled between the drain and gate electrodes.