Integrated multichip memory module structure

• US 5,502,667 A
• Filed: 09/13/1993
• Issued: 03/26/1996
• Est. Priority Date: 09/13/1993
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kalter, Howard K., Kelley, Gordon A. Jr., Bertin, Claude L., Hedberg, Erik L., Howell, Wayne J.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Hoang, Huan
• Application Number:
  US08/120,876
• Time in Patent Office: 925 Days
• Field of Search: 365/51, 365/63, 365/52, 257/686, 257/724, 257/777, 361/684, 361/735, 361/728
• US Class Current: 365/51
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4911 the connectors being bonded to at least one common bonding area, e.g. daisy chain
• CPC Class Codes: H01L 2224/85207 Thermosonic bonding
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01058 : Cerium [Ce]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19107 : off-chip wires

Abstract

An integrated multichip memory module structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the appearance of a single, higher level memory chip. A memory subunit is formed having N memory chips with each memory chip of the subunit having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N×M memory devices appears at the module'"'"'s I/O pins. A preformed electrical interface layer is employed at one end of the memory subunit to electrically interconnect the controlling logic chip with the memory chips comprising the subunit. The controlling logic chip has smaller dimensions than the dimensions of the memory chips comprising the subunit. A lead frame, having an inner opening extending therethrough, is secured to the electrical interface layer and the controlling logic chip is secured to the electrical interface layer so as to reside within the lead frame, thereby producing a dense multichip integrated circuit package. Corresponding fabrication techniques include an approach for facilitating metallization patterning on the side surface of the memory subunit.

Claims

1. An integrated multichip memory module which emulates to external circuitry a single chip memory architecture, said integrated multichip memory module comprising:

a memory subunit having N memory chips (wherein N≧

2), each memory chip of the memory subunit having M memory devices (wherein M≧

2), along with two substantially parallel planar main surfaces and an edge surface, at least one planar main surface of each memory chip being coupled to a planar main surface of an adjacent memory chip of the memory subunit such that said memory subunit has a stack structure; and

logic means electrically connected to each of the N memory chips for coordinating external circuitry communication with said N memory chips of said memory subunit such that an integrated memory architecture with said N×

M memory devices exists which appears to said external circuitry to comprise said single chip memory structure with N×

M memory devices; and

wherein said memory subunit further includes a logic chip, said logic chip having two substantially parallel planar main surfaces, one of said planar main surfaces of said logic chip being coupled to a planar main surface of an adjacent memory chip of the memory subunit, said logic chip being separate from said logic means.

2. An integrated multichip memory module which emulates to external circuitry a single chip memory architecture, said integrated multichip memory module comprising:

a memory subunit having N memory chips (wherein N≧

2), each memory chip of the memory subunit having M memory devices (wherein M≧

2), along with two substantially parallel planar main surfaces and an edge surface, at least one planar main surface of each memory chip being coupled to a planar main surface of an adjacent memory chip of the memory subunit such that said memory subunit has a stack structure; and

logic means electrically connected to each of the N memory chips for coordinating external circuitry communication with said N memory chips of said memory subunit such that an integrated memory architecture with said N×

M memory devices exists which appears to said external circuitry to comprise said single chip memory structure with N×

M memory devices; and

wherein the logic means comprises at least two logic chips mechanically coupled to the memory subunit.

3. An integrated multichip memory module which emulates to external circuitry a single chip memory architecture, said integrated multichip memory module comprising:

a memory subunit having N memory chips (wherein N≧

2), each memory chip of the memory subunit having M memory devices (wherein M≧

2), along with two substantially parallel planar main surfaces and an edge surface, at least one planar main surface of each memory chip being coupled to a planar main surface of an adjacent memory chip of the memory subunit such that said memory subunit has a stack structure; and

logic means electrically connected to each of the N memory chips for coordinating external circuitry communication with said N memory chips of said memory subunit such that an integrated memory architecture with said N×

M memory devices exists which appears to said external circuitry to comprise said single chip memory structure with N×

M memory devices; and

wherein the logic means includes non-semiconductor type devices coupled to said memory subunit.

4. A multichip integrated circuit package comprising:

a plurality of semiconductor chips of similar dimensions coupled together in a stack having an end surface and at least one side surface;

a lead frame secured to the stack at its end surface, said lead frame having an inner opening extending therethrough such that a portion of the stack'"'"'s end surface remains exposed;

a semiconductor chip of smaller dimensions than the similar dimensions of the plurality of semiconductor chips forming the stack, the semiconductor chip of smaller dimensions residing within the inner opening of the lead frame and being secured to the portion of the stack'"'"'s end surface remaining exposed; and

metallurgy means for electrically interconnecting the plurality of semiconductor chips forming the stack, the semiconductor chip of smaller dimensions and the lead frame such that a dense multichip integrated circuit package is defined from semiconductor chips having different dimensions.

5. The multichip integrated circuit package of claim 4, wherein each semiconductor chip of said plurality of semiconductor chips comprises one of a logic chip, a memory chip, and a combination memory and logic chip.

6. The multichip integrated circuit package of claim 4, wherein said semiconductor chip of smaller dimensions includes communication means for coordinating communication between said plurality of semiconductor chips and external circuitry.

7. The multichip integrated circuit package of claim 4, wherein each semiconductor chip of said plurality of semiconductor chips has planar surfaces and a rectangular shape with four side surfaces, and wherein said lead frame also has planar surfaces and a rectangular shape with four side surfaces, the side surfaces of said lead frame being coplanar to the sides surfaces of the plurality of semiconductor chips coupled together in said stack, wherein said multichip integrated circuit package is parallelepiped.

8. The multichip integrated circuit package of claim 4, wherein said lead frame has a first upper surface and wherein said semiconductor chip of smaller dimensions has a second upper surface, said second upper surface being spaced from the stack'"'"'s end surface at least as far as said first upper surface is spaced from said stack'"'"'s end surface.

9. The multichip integrated circuit package of claim 8, wherein said first upper surface and said second upper surface are coplanar.

10. The multichip integrated circuit package of claim 4, wherein said metallurgy means includes a plurality of transfer metallurgies electrically connected to said plurality of semiconductor chips, each transfer metallurgy being connected to one of said semiconductor chips of said plurality of semiconductor chips and extending to the at least one side surface of said stack, and wherein said metallurgy means further includes a first metallurgy pattern disposed on the at least one side surface of the stack, said first metallurgy pattern interconnecting said transfer metallurgies extending to the at least one side surface of the stack such that the plurality of semiconductor chips are electrically interconnected.

11. The multichip integrated circuit package of claim 10, wherein said metallurgy means further includes an electrical interface layer connected to the end surface of said stack between said stack and said lead frame, said electrical interface layer including a second metallurgy pattern, said second metallurgy pattern electrically connecting with said first metallurgy pattern on the at least one side surface of the stack.

12. The multichip integrated circuit package of claim 11, wherein said electrical interface layer has two substantially parallel planar main surfaces and an edge surface, one of said substantially parallel planar main surfaces of said electrical interface layer comprising a lower main surface and the other main surface of said two substantially parallel planar main surfaces comprising an upper main surface, and wherein said second metallurgy pattern includes a lower surface layer of interconnect metallurgy extending to said at least one side surface having said first metallurgy pattern disposed thereon, and an upper surface layer of interconnect metallurgy, said upper surface layer of interconnect metallurgy electrically connecting with said semiconductor chip of smaller dimensions, said electrical interface layer further including metallized throughholes extending between said substantially parallel planar main surfaces to electrically interconnect said lower surface layer of interconnect metallurgy and said upper surface layer of interconnect metallurgy.

13. The multichip integrated circuit package of claim 11, wherein said second metallurgy pattern electrically connects with said semiconductor chip of smaller dimensions such that the semiconductor chip of smaller dimensions and the semiconductor chips of similar dimensions forming the stack are electrically interconnected.

14. The multichip integrated circuit package of claim 13, wherein said second metallurgy pattern electrically connects with said semiconductor chip of smaller dimensions via one of solder bumps and conventional wirebonding without use of T-connect on the semiconductor chip of smaller dimensions.

15. The multichip integrated circuit package of claim 13, wherein said metallurgy means further includes wirebonding electrically interconnecting said lead frame and said semiconductor chip of smaller dimensions.

16. An integrated multichip memory module comprising:

N memory chips (wherein N≧

2) each having M memory devices (wherein M≧

2), each memory chip also having two substantially parallel planar main surfaces and an edge surface, said N memory chips being stacked together to form a subunit having at least one side surface and an end surface, the at least one side surface of the subunit being defined by the edge surfaces of the N memory chips, and the end surface of the subunit extending parallel to the planar main surfaces of the N memory chips forming the subunit, at least some of said N memory chips including transfer metallurgy extending to the at least one side surface of the subunit;

a first metallization pattern disposed on said subunit'"'"'s at least one side surface and electrically connecting with the transfer metallurgy extending to the at least one side surface of the subunit;

an electrical interface layer disposed adjacent to the end surface of the subunit, said electrical interface layer having two substantially parallel planar main surfaces and an edge surface, one of said substantially parallel planar main surfaces of said electrical interface layer being coupled to the end surface of the subunit, the edge surface of the electrical interface layer aligning with the at least one side surface of said subunit, said electrical interface layer having a second metallization pattern disposed therethrough, said second metallization pattern electrically connecting with said first metallization pattern on the at least one side surface of the subunit; and

a logic chip mechanically coupled to an exposed planar main surface of the electrical interface layer and electrically connected to said second metallization pattern such that said logic chip is electrically connected to the memory chips having said transfer metallurgy extending to the at least one side surface of the subunit through said first and second metallization patterns, said logic chip including means for coordinating external communication with said N memory chips of said subunit.

17. The integrated multichip memory module of claim 16, wherein the memory module communicates with a memory controller, said memory controller providing an address signal to said logic chip, and wherein said logic chip includes logic means for decoding the address signal to identify a particular memory chip of said N memory chips in said subunit having the memory device addressed by the address signal.

18. The integrated multichip memory module of claim 16, wherein said logic chip includes logic means for sequentially refreshing each of said N memory chips of the subunit.

19. The integrated multichip memory module of claim 18, wherein said logic means for sequentially refreshing includes a counter connected for sequentially tracking refreshing of each of said N memory chips of said subunit.

20. The integrated multichip memory module of claim 16, wherein the memory module communicates with a memory controller, and wherein said logic chip further includes logic means for initiating a sleep mode within each of said N memory chips of the subunit in response to a sleep command received from the memory controller.

21. The integrated multichip memory module of claim 16, wherein said logic chip further includes voltage regulation means for transforming a received voltage to an on-chip voltage for powering said logic chip.

22. The integrated multichip memory module of claim 16, further comprising a lead frame having a central opening extending therethrough sufficiently sized to accommodate said logic chip therein, said lead frame being coupled to said electrical interface layer such that said logic chip is surrounded by said lead frame, said lead frame facilitating external electrical connection to said logic chip.

23. The integrated multichip memory module of claim 22, wherein N equals four and wherein each of said four memory chips comprises a RAM chip.

24. The integrated multichip memory module of claim 23, wherein said second metallization pattern electrically connects with said logic chip via one of solder bumps and conventional wirebonding without use of T-connects on the logic chip.

25. The integrated multichip memory module of claim 24, wherein said lead frame and said logic chip are electrically interconnected via conventional wirebonding.

26. The integrated multichip memory module of claim 16, further comprising a lead frame electrically connected to said integrated multichip memory module, said lead frame facilitating external electrical connection to said logic chip.