Clock generator capable of shut-down mode and clock generation method

• US 5,502,689 A
• Filed: 02/24/1994
• Issued: 03/26/1996
• Est. Priority Date: 07/21/1992
• Status: Expired due to Term

• Current Assignee: Norman IP Holdings LLC (Altitude Capital Partners)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Hendrickson, Alan F., Gulick, Dale E., Grumlose, Dean, Peterson, Joseph W.
• Primary Examiner(s): Miska, Vit W.
• Application Number:
  US08/201,077
• Time in Patent Office: 761 Days
• Field of Search: 368/10, 368/66, 368/155-157, 368/200-204, 364/707, 395/750
• US Class Current: 368/156
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A clock generator and interrupt bypass circuit for use in reducing the power consumption of the electrical system in which they are implemented. The clock generator provides module clock signals for sequencing modules within the same electrical system, and is capable of generating those module clock signals when in an active mode, and of not generating those module clock signals when in a stand-by mode. The clock generator is further capable of providing a delay of a predetermined length from a request to enter shut-down mode to actual entry into shut-down mode, allowing time to prepare the electrical system for shut-down mode. The interrupt bypass circuit provides a means of leaving shut-down mode in the event that the relevant interrupt requests have been masked.

Claims

1. A clock generator for an electrical system, said clock generator capable of providing at least one output clock signal, said clock generator comprising:

means for producing said at least one output clock signal;

means for disabling said means for producing upon reception of a disable activation signal;

means for receiving a shut-down entry request signal;

means for verifying that said received shut-down entry request signal meets a predetermined protocol requirement, said means for verifying comprising at least two registers, said means for verifying generating said disable activation signal upon verification that a received shut-down entry request signal does meet said predetermined protocol requirement, which disable activation signal is conducted to said means for disabling.

2. A clock generator as recited in claim 1, wherein said means for verifying further comprises an interlock mechanism capable of detecting writes to said at least two registers, and wherein one of said at least two registers is a dummy register.

3. A clock generator as recited in claim 2, wherein said interlock mechanism prevents write access to one of said at least two registers unless said predetermined protocol requirement is met.

4. A clock generator as recited in claim 3, wherein said predetermined protocol requirement comprises a predetermined number of writes in a predetermined order to said at least two registers.

5. A method for controlling at least one output clock signal comprising the steps of:

receiving a disable request signal;

stopping said at least one output clock signal after a predetermined length of time after receiving said disable request signal;

receiving an enable request signal; and

starting said at least one output clock signal after receiving said enable request signal,

wherein said step of stopping said at least one output clock signal comprises the steps of verifying that said disable request signal satisfies a predetermined protocol requirement, and processing said disable request signal only if said disable request signal satisfies said predetermined protocol requirement.

6. A method as recited in claim 5 wherein said step of starting said at least one output clock signal comprises the steps of:

starting a first clock signal; and

starting said at least one output clock signal after a delay following said step of starting said first clock signal, said at least one output clock signal being derived from said first clock signal.

7. A method as recited in claim 5 wherein said step of stopping said at least one output clock signal comprises the step of not stopping said at least one output clock signal if said enable request signal is received after receiving said disable request signal and before the expiration of said predetermined length of time.

8. A method as recited in claim 5 wherein the step of stopping said at least one output clock signal comprises the step of stopping said at least one output clock signal after said predetermined length of time following the most recent assertion of said disable request signal.

9. A method as recited in claim 5 further comprising the step of generating said enable request signal in response to at least one interrupt request signal, said enable request signal being generated even if said at least one interrupt request signal has been masked.