Clock generator capable of shut-down mode and clock generation method
DC CAFCFirst Claim
1. A clock generator for an electrical system, said clock generator capable of providing at least one output clock signal, said clock generator comprising:
- means for producing said at least one output clock signal;
means for disabling said means for producing upon reception of a disable activation signal;
means for receiving a shut-down entry request signal;
means for verifying that said received shut-down entry request signal meets a predetermined protocol requirement, said means for verifying comprising at least two registers, said means for verifying generating said disable activation signal upon verification that a received shut-down entry request signal does meet said predetermined protocol requirement, which disable activation signal is conducted to said means for disabling.
11 Assignments
Litigations
1 Petition
Reexamination
Accused Products
Abstract
A clock generator and interrupt bypass circuit for use in reducing the power consumption of the electrical system in which they are implemented. The clock generator provides module clock signals for sequencing modules within the same electrical system, and is capable of generating those module clock signals when in an active mode, and of not generating those module clock signals when in a stand-by mode. The clock generator is further capable of providing a delay of a predetermined length from a request to enter shut-down mode to actual entry into shut-down mode, allowing time to prepare the electrical system for shut-down mode. The interrupt bypass circuit provides a means of leaving shut-down mode in the event that the relevant interrupt requests have been masked.
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Citations
9 Claims
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1. A clock generator for an electrical system, said clock generator capable of providing at least one output clock signal, said clock generator comprising:
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means for producing said at least one output clock signal; means for disabling said means for producing upon reception of a disable activation signal; means for receiving a shut-down entry request signal; means for verifying that said received shut-down entry request signal meets a predetermined protocol requirement, said means for verifying comprising at least two registers, said means for verifying generating said disable activation signal upon verification that a received shut-down entry request signal does meet said predetermined protocol requirement, which disable activation signal is conducted to said means for disabling. - View Dependent Claims (2, 3, 4)
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5. A method for controlling at least one output clock signal comprising the steps of:
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receiving a disable request signal; stopping said at least one output clock signal after a predetermined length of time after receiving said disable request signal; receiving an enable request signal; and starting said at least one output clock signal after receiving said enable request signal, wherein said step of stopping said at least one output clock signal comprises the steps of verifying that said disable request signal satisfies a predetermined protocol requirement, and processing said disable request signal only if said disable request signal satisfies said predetermined protocol requirement. - View Dependent Claims (6, 7, 8, 9)
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Specification