Path allocation system and method having double link list queues implemented with a digital signal processor (DSP) for a high performance fiber optic switch

• US 5,502,719 A
• Filed: 10/27/1994
• Issued: 03/26/1996
• Est. Priority Date: 10/27/1994
• Status: Expired due to Fees

• Current Assignee: Mcdata Corporation (Broadcom, Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Grant, Robert H., Book, David, Stoevhase, Bent, Purohit, Robin
• Primary Examiner(s): MARCELO, MELVIN C
• Application Number:
  US08/330,044
• Time in Patent Office: 516 Days
• Field of Search: 370/58.1, 370/58.2, 370/58.3, 370/60, 370/60.1, 370/61, 370/85.6, 370/94.1, 370/94.2, 359/117, 395/250
• US Class Current: 370/412
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/357 Fibre channel switches

Abstract

A fiber optic switch interconnects ports (p1-pi) for connection with respective fiber optic channels so that a fiber optic network is realized. Channel modules provide the ports. Each channel module has a port intelligence mechanism for each port and a memory interface system for temporarily storing data passing to and from the ports. A switch module having a main distribution network, an intermix distribution network, and a control distribution network interconnects the memory interface systems and permits exchange of data among the ports and memory interface systems. A path allocation system controls the switch module and allocates the data paths therethrough. The path allocation system has a scheduler which maintains a destination queue (Q_p1 -Q_pi) for each of the ports. The destination queues are implemented with a double link list in a single memory configuration so that a separate queue structure in hardware is not necessary. Moreover, the scheduler is implemented with a digital signal processor (DSP) with on-chip memory so that the queues are implemented within the on-chip memory and can be accessed at high speed.

Claims

1. A path allocation system for allocating paths through a fiber optic switch for interconnecting fiber optic ports, comprising:

a queue corresponding to each of said ports, each said queue for storing addresses received from said ports and identifying data destined for a corresponding port, said addresses being arranged in an order by a link list wherein each of said addresses has an associated pointer indicating a successive address; and

a processor for controlling said queues, said processor for storing said addresses received from said ports in said queues, said processor for generating and storing said pointers in said queues, said processor for retrieving addresses from said queues in said order defined by said link list, and said processor for causing transfer of data corresponding to said addresses to corresponding ports.

2. The system of claim 1, wherein said link list is a double link list, wherein said associated pointers are forward links of said double link list which identifies a subsequent entry in said order, and further comprising another pointer of said double link list which serves as a backward link to identify a previous queue entry in said order.

3. The system of claim 1, further comprising:

receive memory means for storing incoming data from said ports;

a switch means for communicating data from said memory means to said ports and between ports;

a new event generator connected to said receive memory means and configured to determine when data has been received from said ports, said new event generator for forwarding said addresses to said processor; and

an arbitrator connected to said processor, said arbitrator for receiving transfer requests from said processor and for controlling said switch means pursuant to said transfer requests.

4. The system of claim 1, further comprising a receive buffer associated with each of said fiber optic ports directed to storing incoming data from each of said ports and wherein each of said addresses comprises a source port indicator which identifies a source port and a buffer indicator which identifies a particular receive buffer associated with said source port where data resides.

5. The system of claim 1, wherein said processor is a digital signal processor.

6. The system of claim 1, wherein said processor resides on a discrete integrated circuit component and wherein said queues reside in memory on said discrete integrated circuit component.

7. The system of claim 1, wherein each of said addresses includes a class indicator which identifies when data is to be transferred between ports via a frame transfer and via a reserved path transfer.

8. The system of claim 2, wherein said double link list implements a first-in-first-out procedure for said addresses stored in said destination queues.

9. The system of claim 2, further comprising a means associated with said processor for deleting an entry within said double link list of one of said queues by modifying said forward and said backward links associated with said entry.

10. A system for implementing a high performance fiber optic switch for a fiber optic network, comprising:

a plurality of fiber optic ports;

receive memory means for storing incoming data from said ports;

a switch means for communicating data from said memory means to said ports;

a queue corresponding to each of said ports, each said queue for storing addresses received from said ports and identifying data destined for a corresponding port, said addresses being arranged in an order by a link list wherein each of said addresses has an associated pointer indicating a successive address; and

a scheduler configured to control said queues and said switch means, said scheduler configured to store said addresses received from said ports in said queues, said scheduler configured to generate and store said link list, said scheduler configured to retrieve said addresses from said queues in said order defined by said link list, and said scheduler configured to initiate transfer of data corresponding to said addresses to corresponding ports via said switch means.

11. The system of claim 10, wherein said link list is a double link list, wherein said associated pointer is a forward link of said double link list which identifies a subsequent entry in said order, and further comprising another pointer of said double link list which serves as a backward link to identify a previous queue entry in said order.

12. The system of claim 10, wherein said receive memory means comprises a plurality of receive memories, each of said receive memories comprising a plurality of buffers, and wherein each of said addresses comprises a source port indicator which identifies said receive memory and a buffer indicator which identifies a particular buffer within said receive memory where data resides.

13. The system of claim 10, wherein said scheduler is a digital signal scheduler.

14. The system of claim 10, wherein said scheduler comprises a processor situated on a discrete integrated circuit component and wherein said plurality of destination queues resides in a memory situated on said discrete integrated circuit component.

15. The system of claim 10, wherein each of said addresses includes a class indicator which identifies when data is to be transferred between ports via a frame transfer and via a reserved path transfer.

16. The system of claim 11, wherein said double link list implements a first-in-first-out buffer for said addresses stored in said destination queues.

17. The system of claim 11, further comprising a means associated with said scheduler for deleting a queue entry within said queues by modifying said forward and said backward links.

18. A method for implementing a high performance fiber optic switch for interconnecting fiber optic channels in a fiber optic network, comprising the steps of:

receiving data and a destination indicator from a source port, said destination indicator identifying a destination port;

storing said data at a location;

storing a queue entry in a queue corresponding to said destination port, said queue entry identifying said location;

defining said queue with a link list;

retrieving said entry from said queue based upon an order defined by said link list; and

communicating data corresponding to said entry from said source port to said destination port.

19. The method of claim 18, wherein said link list is a double link list.

20. The method of claim 19, wherein said order is a first-in-first-out procedure.