Method of producing semiconductor integrated circuit device having memory cell and peripheral circuit MISFETs

• US 5,504,029 A
• Filed: 06/06/1994
• Issued: 04/02/1996
• Est. Priority Date: 09/19/1987
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Hiraiwa, Atsushi, Shimizu, Shinji, Murata, Jun, Asano, Isamu, Sugiura, Jun, Sagawa, Masakazu, Tadaki, Yoshitaka, Sekiguchi, Toshihiro, Kaneko, Hiroko, Ogishi, Hidetsugu, Horiuchi, Mitsuaki, Ozawa, Masami
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): TSAI, H JEY
• Application Number:
  US08/254,562
• Time in Patent Office: 666 Days
• Field of Search: 437/47, 437/52, 437/60, 437/919
• US Class Current: 438/241
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor

Abstract

A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. The impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. The Y-select signal line overlaps the lower electrode layer of the capacitor element. A potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. The dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it. The capacitor dielectric film is a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure. An aluminum wiring layer and a protective (and/or barrier) layer are formed by sputtering in the same vacuum sputtering chamber without breaking the vacuum between forming the layers; and a refractory metal, or a refractory metal silicide QSi_x, where Q is a refractory metal and x is between 0 and 2, is used as a protective layer, for an aluminum wiring containing an added element (e.g., Cu) to prevent migration.

Claims

1. A method of manufacturing a semiconductor integrated circuit device having (1) memory cells each comprising a first MISFET and a capacitor element connected in series and (2) a peripheral circuit comprising second MISFETs, comprising the steps of:

providing a semiconductor substrate having a main surface of first conductivity type, said main surface including a first area for forming one of said memory cells and a second area for forming one of said second MISFETs;

forming a first conductive strip, having two sides, both said two sides overlying said first area, as a gate electrode for said first MISFET, and forming a second conductive strip, having two sides, both said two sides overlying said second area as a gate electrode for a second MISFET;

introducing first impurities of second conductivity type, which is opposite to said first conductivity type, into said semiconductor substrate in said first and second areas, in a self-aligned manner with said first and second conductive strips, thereby to form first semiconductor regions as source and drain regions for said first MISFET in said first area and second semiconductor regions in said second area as source and drain regions for said second MISFET;

selectively forming sidewall spacers on both sides of each of said first and second conductive strips;

forming a first insulating film over said first and second conductive strips in said first and second areas, said first insulating film having a via exposing said sidewall spacers on sides of said first conductive strips and exposing a surface portion of said semiconductor substrate into which said first impurities have been introduced in said first area;

forming a first polycrystalline silicon strip in said via so that said first polycrystalline silicon strip contacts said surface portion in said first area;

forming a dielectric film over said first polycrystalline silicon strip and forming a third conductive strip over said dielectric film; and

introducing second impurities of second conductivity type into said semiconductor substrate in said second area in a self-aligned manner with said sidewall spacers, on both sides of said second conductive strip, without introducing said second impurities in said first area, thereby to form third semiconductor regions as source and drain regions of said second MISFET, wherein said step of introducing second impurities is performed using second impurities having higher impurity concentration than said first impurities so as to form said third semiconductor regions having a higher impurity concentration than that of said first semiconductor regions.

2. A method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising a step of forming a mask layer covering said first area and exposing said second area, prior to said introducing second impurities, said mask layer acting as a mask when introducing the second impurities.

3. A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said step of forming sidewall spacers comprises the substeps of:

forming an insulating film over said first and second conductive strips; and

etching said insulating film by using reactive ion etching.

4. A method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising a step of forming a fourth conductive strip in said first area, said fourth conductive strip being connected to another of said source and drain regions of said first MISFET.

5. A method of manufacturing a semiconductor integrated circuit device according to claim 4, further comprising a step of forming fifth conductive strips in said second area, said fifth conductive strips being connected to said source and drain regions of said second MISFET.

6. A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first polycrystalline silicon film is formed in a self-aligned manner in contact with said surface portion exposed in said via.

7. A method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising the step of introducing third impurities of the second conductivity type in said surface portion so as to form a fourth semiconductor region in one of said first semiconductor regions, the fourth semiconductor region having a higher impurity concentration than said one of the first semiconductor regions.

8. A method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein said third impurities are introduced in said surface portion by diffusion from the first polycrystalline silicon strip, the third impurities having been included in the first polycrystalline silicon strip.

9. A method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein the impurity concentration of the fourth semiconductor region is less than an impurity concentration of the third semiconductor regions.

10. A method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein a depth of the fourth semiconductor region from the main surface of the semiconductor substrate is less than that of the first semiconductor regions.

11. A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first polycrystalline silicon strip is a conductive strip having said third impurities therein.

12. A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first polycrystalline silicon strip contacts with one of the first semiconductor regions, and wherein the method includes the further step of forming a conductive line connected with another of the first semiconductor regions, the further step of forming the conductive line including substeps of:

forming a fifth semiconductor region in said another of the first semiconductor regions, the fifth semiconductor region being of a same conductivity type as that of the first semiconductor regions and of a higher impurity concentration than that of the first semiconductor regions; and

forming the conductive line so as to contact the fifth semiconductor region.

13. A method of manufacturing a semiconductor integrated circuit device according to claim 12, wherein the fifth semiconductor region is formed by introducing impurities into said another of the first semiconductor regions via a contact hole exposing said another of the first semiconductor regions, and wherein the conductive line is formed so as to extend into said contact hole.

14. A method of manufacturing a semiconductor integrated circuit device according to claim 13, wherein the impurities are introduced into said another of the first semiconductor regions, to form the fifth semiconductor region, by ion implantation.

15. A method of manufacturing a semiconductor integrated circuit device according to claim 12, wherein, prior to forming the conductive line, an inter-layer insulating film is selectively removed so as to expose the semiconductor substrate at the fifth semiconductor region, the inter-layer insulating film being selectively removed using the third conductive strip as a mask.

16. A process for forming a first MISFET and second MISFETs of a semiconductor integrated circuit device having (1) memory cells each comprising the first MISFET and a capacitor element connected in series and (2) a peripheral circuit comprising the second MISFETs, comprising the steps of:

providing a semiconductor substrate having a main surface of a first conductivity type, said main surface including a first area for forming one of said memory cells and a second area for forming a second MISFET of said second MISFETs;

forming a first conductive strip, having two sides, both said two sides overlying said first area, as a gate electrode for said first MISFET, and forming a second conductive strip, having two sides, both said two sides of said second conductive strip overlying said second area, as a gate electrode for said second MISFET;

introducing first impurities of a second conductivity type, which is opposite to said first conductivity type, into said semiconductor substrate in said first and second areas, in a self-aligned manner with said first and second conductive strips, thereby to form first semiconductor regions as source and drain regions for said first MISFET in said first area, and second semiconductor regions in said second area;

selectively forming sidewall spacers on both sides of each of said first and second conductive strips;

forming a first insulating film over said first and second conductive strips in said first and second areas, said first insulating film having a via exposing said sidewall spacers formed on said first conductive strip and exposing a surface portion of said semiconductor substrate into which said first impurities have been introduced in said first area;

forming a first polycrystalline silicon strip in said via so that said first polycrystalline silicon strip contacts with said surface portion in said first area;

forming a mask layer which covers said first area and exposes said second area; and

introducing second impurities of the second conductivity type into said semiconductor substrate in said second area in self-aligned manner with said sidewall spacers, on both sides of said second conductive strip, by using said mask layer as a mask, thereby to form third semiconductor regions as source and drain regions of said second MISFET,

wherein said step of introducing second impurities is performed using second impurities having higher impurity concentration than said first impurities, such that the third semiconductor regions have a higher impurity concentration than that of said first semiconductor regions.

17. A process according to claim 16, further comprising the step of introducing third impurities of the second conductivity type in said surface portion so as to form a fourth semiconductor region in one of said first semiconductor regions, the fourth semiconductor region having a higher impurity concentration than said one of the first semiconductor regions.

18. A process according to claim 17, wherein said third impurities are introduced in said surface portion by diffusion from the first polycrystalline silicon strip, the third impurities having been included in the first polycrystalline silicon strip.

19. A process according to claim 18, wherein said first polycrystalline silicon strip is connected to said capacitor element.

20. A process according to claim 17, wherein the impurity concentration of the fourth semiconductor region is less than an impurity concentration of the third semiconductor regions.

21. A process according to claim 17, wherein a depth of the fourth semiconductor region from the main surface of the semiconductor substrate is less than that of the first semiconductor regions.

22. A process according to claim 16, wherein the first polycrystalline silicon strip contacts with one of the first semiconductor regions, and wherein the method includes the further step of forming a conductive line connected with another of the first semiconductor regions, the further step of forming the conductive line including substeps of:

forming a fifth semiconductor region in said another of the first semiconductor regions, the fifth semiconductor region being of a same conductivity type as that of the first semiconductor regions and of a higher impurity concentration than that of the first semiconductor regions; and

forming the conductive line so as to contact the fifth semiconductor region.

23. A process according to claim 22, wherein the fifth semiconductor region is formed by introducing impurities into said another of the first semiconductor regions via a contact hole exposing said another of the first semiconductor regions, and wherein the conductive line is formed so as to extend into said contact hole.