Dynamic random access memory having a vertical transistor
First Claim
1. A dynamic random access memory having a vertical transistor, comprising:
- a silicon substrate having an upper surface and having a trench having a bottom surface, a wall surface, and an opening at the upper surface of the silicon substrate;
a bit line junction region extending into the silicon substrate from said bottom surface and from a lower region of said wall surface that is adjacent to said bottom surface;
a bit fine at said bottom surface of the trench and connected to said bitline junction region;
a word line formed in the trench and insulated from said bit line by a first insulating layer, and insulated from the wall surface by a gate oxide layer formed on the wall surface, whereby a vertical channel region is defined in the semiconductor substrate along the gate oxide layer under the word line;
a charge storage electrode junction region extending from a region of the wall surface near the opening at the upper surface and connected to said channel region and formed below the surface of said silicon substrate;
a pad polysilicon layer connected to the upper part of said charge storage electrode junction region and insulated from said word line via a second insulating layer;
a charge storage electrode connected to said pad polysilicon layer, whereby when a voltage is applied to said word line, said vertical channel region is formed so that a signal transmitter is transferred from said bit line to said charge storage electrode.
0 Assignments
0 Petitions
Accused Products
Abstract
A DRAM having a vertical transistor of a highly integrated semiconductor device and its manufacturing method are disclosed. A DRAM has a silicon substrate, a word line formed in a silicon substrate, a gate oxide layer formed on the side wall of the word line, a bit line junction region formed on the bottom of a silicon substrate, a bit line that is connected to the a bit line junction region and is insulated from the word line via a first insulating layer, a charge storage electrode junction region formed near the bottom of silicon substrate surface, a pad polysilicon layer that is insulated from the a word line via a second insulating layer and is connected at the top of a charge storage electrode diffusion region, and a charge storage electrode that is connected to the pad polysilicon layer through a contact. Accordingly, a channel region is formed on a silicon substrate positioned on the side wall of a word line by applying the voltage to the word line and thus a signal transmitter is mutually transferred from the bit line to the charge storage electrode.
143 Citations
9 Claims
-
1. A dynamic random access memory having a vertical transistor, comprising:
-
a silicon substrate having an upper surface and having a trench having a bottom surface, a wall surface, and an opening at the upper surface of the silicon substrate; a bit line junction region extending into the silicon substrate from said bottom surface and from a lower region of said wall surface that is adjacent to said bottom surface; a bit fine at said bottom surface of the trench and connected to said bitline junction region; a word line formed in the trench and insulated from said bit line by a first insulating layer, and insulated from the wall surface by a gate oxide layer formed on the wall surface, whereby a vertical channel region is defined in the semiconductor substrate along the gate oxide layer under the word line; a charge storage electrode junction region extending from a region of the wall surface near the opening at the upper surface and connected to said channel region and formed below the surface of said silicon substrate; a pad polysilicon layer connected to the upper part of said charge storage electrode junction region and insulated from said word line via a second insulating layer; a charge storage electrode connected to said pad polysilicon layer, whereby when a voltage is applied to said word line, said vertical channel region is formed so that a signal transmitter is transferred from said bit line to said charge storage electrode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
Specification