Demodulator for powerline carrier communications
First Claim
1. A method of demodulating an HDLC data body which had been modulated through differential phase shift keyed modulation, the method comprises the steps of:
- sampling the data body in a sampling flip-flop which splits the data body into first and second identical portions;
inputting the first portion of the data body into a single bit digital delay circuit which outputs a previous binary data bit;
inputting the second portion of the previous binary data bit into a first input of an XNOR circuit;
inputting the data body directly into a secure input of the XNOR circuit so that of the data body, a present data bit and a previous data bit are compared by the XNOR circuit and when the previous binary data bit and the next consecutive binary data bit have unlike phases the XNOR circuit outputs a first binary data bit value, and when the previous binary data bit and the next consecutive binary data bit have like phases, the XNOR circuit outputs a second binary data bit value.
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Abstract
A method for demodulating the carrier signal of powerline communication networks. The method involves demodulating an HDLC data body that had been modulated through differential phase shift keyed modulation. Under the method, the data body is split with data input into a single bit digital delay circuit which outputs a delayed or "previous" binary data bit. A "present" binary data bit is input to one input of an XNOR circuit and the previous binary data bit is input into a second input of the XNOR circuit. When the present binary data bit and the previous binary data bit have unlike phases the XNOR circuit outputs a first binary data bit value. When the present binary data bit and the previous binary data bit have like phases, the XNOR circuit outputs a second binary data bit value. Preferably, the demodulated data is input into a post detection filter. The demodulation method also preferably involves the step of processing the demodulated data through a receive data correlator, a data body state machine and a variable divide counter.
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Citations
16 Claims
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1. A method of demodulating an HDLC data body which had been modulated through differential phase shift keyed modulation, the method comprises the steps of:
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sampling the data body in a sampling flip-flop which splits the data body into first and second identical portions; inputting the first portion of the data body into a single bit digital delay circuit which outputs a previous binary data bit; inputting the second portion of the previous binary data bit into a first input of an XNOR circuit; inputting the data body directly into a secure input of the XNOR circuit so that of the data body, a present data bit and a previous data bit are compared by the XNOR circuit and when the previous binary data bit and the next consecutive binary data bit have unlike phases the XNOR circuit outputs a first binary data bit value, and when the previous binary data bit and the next consecutive binary data bit have like phases, the XNOR circuit outputs a second binary data bit value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An apparatus for demodulating an HDLC data body which had been modulated by Differential Phase Shift Keyed modulation comprising:
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a sampling flip-flop which splits the data body into first and second identical portions; a single bit digital delay circuit that receives a binary data bit from the first data body portion and outputs a delayed binary data bit; an XNOR circuit having first and second inputs in which a present binary data bit from the second data portion is input into the first XNOR circuit input and the delayed binary bit is input into the second XNOR circuit input, and wherein the XNOR circuit outputs a first binary data bit value when the present binary data bit and the delayed binary data bit have unlike phases, and wherein the XNOR circuit outputs a second binary data bit value when the present binary data bit and the delayed binary data bit have like phases. - View Dependent Claims (13, 14, 15, 16)
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Specification