Television receiver for displaying two pictures of similar or different aspect ratios simultaneously

• US 5,504,535 A
• Filed: 12/22/1994
• Issued: 04/02/1996
• Est. Priority Date: 12/24/1993
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Abe, Hirotoshi
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): HSIA, SHERRIE Y
• Application Number:
  US08/361,483
• Time in Patent Office: 467 Days
• Field of Search: 348/584, 348/586, 348/588, 348/555, 348/556, 348/557, 348/564, 348/565, 348/566, 348/567, 348/568, 348/598, 348/599, 348/445, 348/913, 358/704, 358/183, 358/22, 358/241 P
• US Class Current: 348/565
• CPC Class Codes: H04N 5/45 Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 7/0122 the input and the output signals having different aspect ratios

Abstract

A display is to be produced based on video signals having aspect ratios of 4:3 and 16:9. Controller 21 turns on switches SW1 and SW2 so that the digitalized video signal of the first picture is compressed at a rate of 3/8 in the time axis. Simultaneously, the video signal of the second picture is converted digitally, written into memory 14 in synchronization with the first picture video signal, read out based on a delay of 3H/8 from the synchronization with the first picture video signal, and sent to a digital processing circuit 13. The controller 21 controls the digital processing circuit 13 so as to compress in the time axis the video signal of the second picture at a compressing rate of 5/8. Also, the controller 21 controls a vertical amplitude switching signal generator 19 to adjust a vertical deflecting current in a deflecting circuit 18 based on an operation by the audience.

Claims

1. A television receiver for simultaneously arranging and displaying a first picture having a first aspect ratio and a second picture having a second aspect ratio wider than said first aspect ratio in a wide aspect picture display, comprising:

video signal input means including a first video signal generating means and a second video signal generating means;

first digital converting means for converting a first video signal from said first video signal generating means into a first digital signal;

second digital converting means for converting a second video signal from said second video signal generating means into a second digital signal;

first compressing means including a series arrangement of a first compressing circuit having a first compressing rate and a second compressing circuit having a second compressing rate, said first compressing means receiving said first digital signal from said first digital converting means, compressing said first digital signal in a horizontal time axis at a first total compressing rate using at least one of said first compressing circuit and said second compressing circuit, and outputting a compressed first digital signal;

first analog converting means for converting said compressed first digital signal output from said first compressing means into a first analog signal;

second compressing means including a memory, said second compressing means receiving said second digital signal from said second digital converting means, compressing said second digital signal in the horizontal time axis at a third compressing rate based on said first total compressing rate, writing said compressed second digital signal into said memory, reading said compressed second digital signal from said memory based on a timing signal produced from a synchronized signal of said first video signal, and outputting said compressed second digital signal read from said memory;

second analog converting means for converting said compressed second digital signal output from said second compressing means into a second analog signal;

synthesizing means for synthesizing said first analog signal and said second analog signal, and for feeding a synthesized signal to said wide aspect picture display;

controlling means for controlling said first compressing means and said second compressing means when two pictures are simultaneously displayed in said wide aspect picture display;

deflecting means for scanning said wide aspect picture display based on said synchronized signal of said first video signal; and

vertical amplitude variable means connected to said deflecting means for varying a vertical amplitude of a picture displayed in said wide aspect picture display, wherein

said controlling means operates in a displaying mode when aspect ratios of said first video signal and said second video signal each has said first aspect ratio, said third compressing rate being the same as said first total compressing rate when said controlling means operates in said displaying mode.

2. A television receiver according to claim 1, wherein said first compressing rate of said first compressing circuit is 1/2 and said second compressing rate of said second compressing circuit is 3/4 when said first aspect ratio is 4:

3 and said second aspect ratio is 16;

9.

3. A television receiver according to claim 1, wherein said vertical amplitude varied by said vertical amplitude variable means changes based on said displaying mode.

4. A video processing circuit for displaying two video pictures comprising:

first demodulating means for demodulating a first received picture video signal to generate a first luminance signal, first color difference signals, and a first synchronous signal;

first digital converting means for converting a video signal output from said first demodulating means into a first digital signal;

compressing means for compressing said first digital signal, and for outputting compressed first digital signal, said compressing means including a 1/2 compressing circuit and a 3/4 compressing circuit connected in series, said 1/2 compressing circuit for compressing said first digital signal in a time axis of a horizontal direction at a compressing raze of 1/2, and said 3/4 compressing circuit for compressing said first digital signal in said time axis of said horizontal direction at a compressing rate of 3/4, at least one of said 1/2 and 3/4 compressing circuits being selected via first and second switches provided at output terminals of said 1/2 and 3/4 compressing circuits, respectively;

first analog converting means for converting said compressed first digital signal output from said compressing means into a first converted analog signal, and for outputting a first output picture video signal based on said first converted analog signal;

first matrix means for processing said first output picture video signal from said first analog converting means, for synthesizing said first luminance signal and said first color difference signals, and for outputting first RGB signals;

second demodulating means for demodulating a second received picture video signal to generate a second luminance signal, second color difference signals, and a second synchronous signal;

second digital converting means for converting a video signal output from said second demodulating means into a second digital signal;

a digital processing circuit for receiving said second digital signal from the second digital converting means, for writing said second digital signal into a memory based on said first synchronous signal and said second synchronous signal, for reading said second digital signal from said memory based on said first synchronous signal, for compressing said second digital signal at a predetermined compressing rate, and for outputting a compressed second digital signal;

second analog converting means for converting said compressed second digital signal into a second converted analog signal, and for outputting a second output picture video signal based on said second converted analog signal;

second matrix means for processing said second output picture video signal from the second analog converting means, for synthesizing the second luminance signal and the second color difference signals, and for outputting second RGB signals;

adding means for adding said first RGB signals and said second RGB signals and for outputting an added signal;

a cathode ray tube for displaying a picture based on said added signal with an aspect ratio of at least 16;

9;

deflecting means for varying a vertical amplitude of said picture by controlling an amplitude of a vertical deflecting electric current fed to a deflecting yoke of said cathode ray tube based on said first synchronous signal; and

controlling means for controlling said first and second switches of said compressing means, said predetermined compressing rate of said digital processing circuit, and said vertical deflecting current of said deflecting means based on a displaying mode.

5. A video processing circuit according to claim 4, wherein said first and second switches of said compressing means are switched and said compressing rate of said digital processing circuit is set to 5/8 when said first picture video signal is a video signal having an aspect ratio of 4:

3 and said second picture video signal is a video signal having an aspect ratio of 16;

9.

6. A video processing circuit according to claim 5, wherein said two video pictures divide a display with a ratio of 6:

10 in the horizontal direction of the cathode ray tube.

7. A video processing circuit according to claim 5, wherein said respective aspect ratios of a first picture and a second picture can be adjusted to optimum aspect ratios when said vertical amplitude is adjusted by said deflecting means.

8. A video processing circuit according to claim 4, wherein said controlling means selects only said second switch of said compressing means and interrupts said compressed second digital signal output from said digital processing circuit when only said first picture video signal is to be displayed.