Method and apparatus for allocating resources in a multiprocessor system

• US 5,504,670 A
• Filed: 03/31/1993
• Issued: 04/02/1996
• Est. Priority Date: 03/31/1993
• Status: Expired due to Term

• Current Assignee: Agilent Technologies, Inc., Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Pochowski, Robert J., Adair, David J., Schade, Stephen C., Armstrong, Keath A., Barth, Roger E.
• Primary Examiner(s): Ramirez, Ellis B.
• Assistant Examiner(s): PEESO, THOMAS R
• Application Number:
  US08/040,429
• Time in Patent Office: 1,098 Days
• Field of Search: 371/27, 371/21.1, 371/11.1, 364/134, 395/650, 324/765
• US Class Current: 700/5
• CPC Class Codes: G01R 31/31907 Modular tester, e.g. controlling and coordinating instruments in a bus based architecture
• CPC Class Codes: G01R 31/31908 Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
• CPC Class Codes: G06F 9/5016 the resource being the memory

Abstract

A computer system having multiple processors and multiple resources for use by the processors when executing their assigned tasks. The computer system includes a plurality of sub-controllers which allow the resources within the computer system to be allocated among the processors, such that each of the processors has the resources required to complete its task.

Claims

1. An integrated circuit tester for testing a plurality of integrated circuits at the same time, wherein the plurality of integrated circuits is capable of including a plurality of types of integrated circuits, the tester comprising:

a plurality of processors, wherein each of the plurality of processors executes one of a plurality of test programs designed to test one of the plurality of integrated circuits, such that a plurality of test programs are executed;

a plurality of resources coupled to the plurality of processors, wherein each of the plurality of processors uses the plurality of resources when executing test programs to complete execution of at least one of the plurality of test programs,

wherein each of the plurality of resources is initially allocated to the plurality of processors, such that a separate portion of the plurality of resources is initially mapped to each of the plurality of resources; and

at least one controller to reallocate at least one of the plurality of resources, wherein said at least one of the plurality of resources is reallocated among processors as necessary to execute the plurality of test programs, such that at least one of the plurality of processors gains control of said at least one of the plurality of resources initially allocated to another of said plurality processors to test the integrated circuits.

2. The tester as defined in claim 1 further comprising a bus coupled to the plurality of resources, such that the plurality of resources share a common bus.

3. The tester as defined in claim 1 further comprising a controller for assigning each of the plurality of test programs to the plurality of processors, such that each of the plurality of processors executes one of the plurality of tasks designed to test one of the plurality of integrated circuits.

4. The tester as defined in claim 3 wherein a portion of the plurality of resources are reallocated when each test program is assigned by the controller.

5. The tester as defined in claim 1 wherein test programs executed by at least two of the processors are different, such that the tester tests at least two types of the integrated circuit types at the same time.

6. The tester as defined in claim 1 wherein each of the plurality of processors comprises a sub-controller to control reallocation of resources for said each of the plurality of processors.

7. An integrated circuit tester for testing a plurality of integrated circuits, wherein the plurality of integrated circuits is capable of including a plurality of types of integrated circuits, the tester comprising:

a bus;

a plurality of processors coupled to the bus,

a controller for assigning a plurality of test programs to the plurality of processors, wherein each of the plurality of processors executes one of a plurality of test programs designed to test one of the plurality of integrated circuits, such that the plurality of test programs are executed;

a plurality of resources coupled to the bus and initially allocated to the plurality of processors, such that a portion of the plurality of resources is initially mapped to each of the plurality of processors, wherein each of the plurality of processors requires at least one of the plurality of resources when executing its test program; and

a plurality of sub-controllers for allocating the plurality of resources to each of the plurality of processors, wherein each of the plurality of resources required by one of the plurality of processors to execute said one of a plurality of tasks is allocated to said one of the plurality of processors, such that at least one of the plurality of resources is reallocated to a processor other than said one of the plurality of processors to test the integrated circuits.

8. The tester as defined in claim 7 wherein each of the controllers is associated with one of the plurality of processors and allocates the plurality of resources in response to its associated processing means.

9. The tester as defined in claim 7 wherein the plurality of resources includes a plurality of resource types, and wherein each of the plurality of resource types is allocated to one of the plurality of processors.

10. The tester as defined in claim 7 further comprising a plurality of linear configurable arrays, wherein each of the plurality of linear configurable arrays is coupled to one of the plurality of resources, and wherein each of the plurality of linear configurable arrays is capable of coupling at least one resource to at least one of the plurality of processor through the bus, such that upon allocation of the plurality of resources each of the plurality of linear configurable arrays permits use of only that portion of its resource that is allocated to any of the plurality of processors.

11. An integrated circuit tester for testing a plurality of integrated circuits, wherein the plurality of integrated circuits is capable of including a plurality of types of integrated circuits, the tester comprising:

a bus;

a plurality of linear configurable arrays coupled to the bus;

a plurality of resources coupled to the plurality of linear configurable arrays, such that access to each resource is controlled by one of the plurality of linear configurable arrays;

a plurality of processors coupled to the bus, wherein each of the plurality of processors executes one of a plurality of test programs designed to test one of the plurality of integrated circuits, such that a plurality of test programs are executed, and wherein each of the plurality of processors requires at least one of the plurality of resources to execute its test program; and

a plurality of controllers, each controller associated with one of the plurality of processors for allocating the plurality of resources to each of the plurality of processors, wherein each of the plurality of resources required by one of the plurality of processors to execute said one of a plurality of test programs is allocated to said one of the plurality of processors to perform the integrated circuit testing, wherein at least one of the plurality of resources initially mapped to a processor other than said one of the plurality of processors is reallocated to said one of the plurality of processors.

12. A computer system comprising:

a plurality of processors for executing a plurality of tasks;

a first bus for communication information;

a first plurality of sets of non-dedicated resources coupled to the bus for use by the plurality of processors in executing the plurality of tasks;

a first plurality of controllers coupled to the first plurality of sets of non-dedicated resources and the plurality of processors for allocating each of the non-dedicated resources in the first plurality of sets of non-dedicated resources to one of the plurality of processors, such that each of the plurality of resources required by each of the plurality of processors to execute each of the plurality of tasks is allocated to said each of the plurality of processors.

13. The computer system as defined in claim 12 further comprising:

a second bus for communicating information;

a second plurality of resources coupled to the second bus for use by the plurality of processors in executing the plurality of tasks;

a second plurality of controllers coupled to a respective one of the first plurality of controllers for allocating each of the resources in the second plurality of sets of resources to one of the plurality of processors, wherein each of the first plurality of controllers controls the second plurality of controllers, such that the second plurality of resources are allocated to one of the plurality of processors, such that each of the plurality of resources required by one of the plurality of processors to execute said one of a plurality of tasks is allocated to said one of the plurality of processors.