Single event upset hardened CMOS latch circuit

• US 5,504,703 A
• Filed: 02/01/1995
• Issued: 04/02/1996
• Est. Priority Date: 02/01/1995
• Status: Expired due to Term

• Current Assignee: BAE Systems Information and Electronic Systems Integration Incorporated (BAE Systems Plc)
• Original Assignee: Loral Federal Systems Company
• Inventors: Bansal, Jai P.
• Primary Examiner(s): CLAWSON JR, JOSEPH
• Application Number:
  US08/382,112
• Time in Patent Office: 426 Days
• Field of Search: 365/154, 365/156, 365/190, 365/194, 365/189.05
• US Class Current: 365/156
• CPC Class Codes: G11C 11/4125 Cells incorporating circuit means for protecting against loss of information
• CPC Class Codes: G11C 5/005 Circuit means for protection against loss of information of semiconductor storage devices
• CPC Class Codes: H03K 3/013 Modifications of generator to prevent operation by noise or interference
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00

Abstract

SEU immunity is provided in a cross-coupled CMOS latch circuit by inserting a pair of series connected invertors between the drain node of one CMOS invertor and the gate node of the other CMOS invertor and a pair of series connected invertors between the drain node of the other CMOS invertor and the gate node of the one CMOS invertor. The invertor pairs delay the propagation of a change in voltage induced by an energetic ion strike at the off drain of one invertor to the gates of the transistors making up the other cross coupled invertor. The invertor connected to the gates of the transistors affected by the ion strike help in restoring the circuit to its original state.

Claims

1. A single event upset hardened, bi-stable circuit, comprising in combination:

a first pair of CMOS semiconductor transistors with a common drain node and a common gate node;

a second pair of CMOS semiconductor transistors with a common drain node and a common gate node;

first means including a pair of series connected invertors coupling the common drain node of said first pair of CMOS semiconductor transistors to the common gate node of said second pair of CMOS semiconductor transistors; and

second means including a pair of series connected invertors coupling the common drain node of said second pair of CMOS semiconductor transistors to the common gate node of said first pair of CMOS semiconductor transistors.

2. A single event upset hardened, bi-stable circuit as in claim 1, wherein each of said series connected invertors comprises a pair of CMOS transistors with a common gate node and a common drain node.

3. A single event upset hardened, bi-stable circuit as in claim 2, wherein the channel length and channel width of said pair of CMOS transistors which comprise each of said series connected invertors are selected to provide a predetermined delay to the propagation of a change of state between the common drain node of said first pair of CMOS semiconductor transistors and the common gate node of the second pair of CMOS semiconductor transistors and between the common drain node of the second pair of CMOS semiconductor transistors and the common gate node of the first pair of CMOS semiconductor transistors.

4. A single event upset hardened, bi-stable shift register bit circuit, comprising in combination:

a first bi-stable latch including;

a first pair of CMOS semiconductor transistors with a common drain node and a common gate node;

a second pair of CMOS semiconductor transistors with a common drain node and a common gate node;

first means including a pair of series connected invertors coupling the common drain node of said first pair of CMOS semiconductor transistors to the common gate node of said second pair of CMOS semiconductor transistors; and

second means including a pair of series connected invertors coupling the common drain node of said second pair of CMOS semiconductor transistors to the common gate node of said first pair of CMOS semiconductor transistors;

a second bi-stable latch including;

a third pair of CMOS semiconductor transistors with a common drain node and a common gate node;

a fourth pair of CMOS semiconductor transistors with a common drain node and a common gate node;

third means including a pair of series connected invertors coupling the common drain node of said third pair of CMOS semiconductor transistors to the common gate node of said fourth pair of CMOS semiconductor transistors; and

fifth means including a pair of series connected invertors coupling the common drain node of said fourth pair of CMOS semiconductor transistors to the common gate node of said third pair of CMOS semiconductor transistors.

5. A single event upset hardened, bi-stable shift register bit circuit as in claim 4, wherein each of said series connected invertors comprises a pair of CMOS transistors with a common gate node and a common drain node.

6. A single event upset hardened, bi-stable shift register bit circuit as in claim 5, wherein the channel length and channel width of said pair of CMOS transistors which comprise each of said series connected invertors are selected to provide a predetermined delay to the propagation of a change of state between the common drain node of said first pair of CMOS semiconductor transistors and the common gate node of the second pair of CMOS semiconductor transistors and between the common drain node of the second pair of CMOS semiconductor transistors and the common gate node of the first pair of CMOS semiconductor transistors.