Pulse stuffing synchronization control system

• US 5,504,752 A
• Filed: 10/06/1994
• Issued: 04/02/1996
• Est. Priority Date: 01/20/1992
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited, Nippon Telegraph and Telephone Corporation
• Original Assignee: Fujitsu Limited, Nippon Telegraph and Telephone Corporation
• Inventors: Takagi, Seiichi, Yamakawa, Toshihiro, Okazaki, Takeshi
• Primary Examiner(s): Marcelo, Melvin
• Assistant Examiner(s): VU, HUY DUY
• Application Number:
  US08/319,147
• Time in Patent Office: 544 Days
• Field of Search: 370/102, 370/84, 370/100.1, 370/105.1, 370/105.2, 370/105.4, 370/105.5, 370/109, 370/112, 370/106, 375/371, 375/354, 375/362, 375/373, 375/374, 375/375, 375/376, 348/500, 348/471, 348/472, 348/488
• US Class Current: 370/505
• CPC Class Codes: H04J 3/07 using pulse stuffing for systems with different or fluctuating information rates or bit rates
• CPC Class Codes: H04N 7/56 Synchronising systems therefor

Abstract

A pulse stuffing synchronization control system includes a memory circuit for storing a plurality of items of lower digital hierarchy data input thereto in parallel, a clock generator for generating a writing clock signal and a control clock signal, a data writing controller for writing the plurality of items of the lower digital hierarchy data in synchronism with the writing clock signal, a read clock output circuit for generating a reading clock signal, a pulse stuffing controller for generating stuffing information based on the difference between the phases of a transmission clock signal and the control clock signal generated by the clock generator and for controlling the number of pulses of the writing clock signal based on the stuffing information, and a data read controller for reading out the plurality of items of the lower digital hierarchy data from the memory means in synchronism with the reading clock signal processed by the pulse stuffing controller, so that higher digital hierarchy data is output from said memory means in synchronism with the reading clock signal processed by the pulse stuffing controller.

Claims

1. A data synchronization control system comprising:

memory means for storing a plurality of items of lower digital hierarchy data input thereto in parallel;

clock generating means, responsive to a predetermined sampling clock, for generating a writing clock signal and a control clock signal;

data writing means, coupled to said memory means and said clock generating means, for writing said plurality of items of said lower digital hierarchy data into said memory means in synchronization with the writing clock signal;

read clock generating means for generating a reading clock signal;

pulse stuffing control means, coupled to said clock generating means and said read clock generating means, for generating stuffing information based on a difference between phases of a predetermined external clock signal and the control clock signal generated by said clock generating means, and for generating a modified reading clock signal by selectively suppressing pulses of said reading clock signal in response to said stuffing information; and

data read means, coupled to said memory means and said pulse stuffing control means, for successively and directly reading out said plurality of items of the lower digital hierarchy data from said memory means in synchronization with said modified reading clock signal to directly multiplex said plurality of items of the lower digital hierarchy data into higher digital hierarchy data wherein said multiplexing occurs during said successive reading out of items of the lower digital hierarchy data.

2. The system as claimed in claim 1, wherein a ratio of a frequency of the control signal generated by said clock generating means to a frequency of the predetermined external clock signal is an integer.

3. The system as claimed in claim 1, wherein the higher digital hierarchy data is transmitted in synchronization with a transmission clock signal to a receiver via a transmission line, and wherein the predetermined external clock signal is generated by use of the transmission clock signal.

4. The system as claimed in claim 1, wherein the lower digital hierarchy data input to said memory means is video signal component data sampled in synchronization with the predetermined sampling clock signal.

5. The system as claimed in claim 1, wherein the control signal generated by said clock generating means has a transmission rate corresponding to an average transmission rate for data obtained by multiplexing the plurality of items of said lower digital hierarchy data.

6. The system as claimed in claim 1, wherein said memory means comprises a plurality of FIFO memories, each FIFO memory receiving data corresponding to one of said plurality of items of the lower digital hierarchy data.

7. The system as claimed in claim 1, wherein said pulse stuffing control means comprises phase comparator means for outputting stuffing information corresponding to the difference between the phases of the predetermined external clock signal and the control signal, and control means for selectively suppressing pulses of the reading clock signal in accordance with the stuffing information.

8. The system as claimed in claim 7, wherein said phase comparator means comprises a counter for counting a number of pulses of the control clock signal in each cycle of the predetermined external clock signal, and wherein a counting value of said counter is used as the stuffing information.

9. A data synchronization control system comprising:

memory means for storing a plurality of items of lower digital hierarchy data input thereto in parallel;

clock generating means, responsive to a predetermined sampling clock, for generating a writing clock signal and a control clock signal;

data writing means, coupled to said memory means and said clock generating means, for writing said plurality of items of said lower digital hierarchy data into said memory means in synchronization with the writing clock signal;

read clock generating means for generating a reading clock signal;

pulse stuffing control means, coupled to said clock generating means and said read clock generating means, for generating stuffing information based on a difference between phases of a predetermined external clock signal and the control clock signal generated by said clock generating means, and for generating a modified reading clock signal by selectively suppressing pulses of said reading clock signal in response to said stuffing information; and

data read means, coupled to said memory means and said pulse stuffing control means, for successively reading out said plurality of items of the lower digital hierarchy data from said memory means in synchronization with said modified reading clock signal to multiplex said plurality of items into higher digital hierarchy data;

wherein said pulse stuffing control means comprises phase comparator means for outputting stuffing information corresponding to the difference between the phases of the predetermined external clock signal and the control signal, and control means for selectively suppressing pulses of the reading clock signal in accordance with the stuffing information; and

wherein a ratio of a frequency of the writing clock signal to a frequency of the predetermined external clock signal is not an integer and the writing clock signal is used as the control signal, and wherein said phase comparator means comprises first means for calculating data corresponding to a difference between the control signal and the predetermined clock signal, and second means for correcting the data calculated by said first means based on the ratio of the frequency of the writing clock signal to the frequency of the predetermined external clock signal, so that the data corrected by said second means is output as the stuffing information from said phase comparator means.

10. The system as claimed in claim 9, wherein said first means comprises a counter for counting a number of pulses of the control signal in each cycle of the predetermined external clock signal, a count value of said counter being supplied to said second means.

11. The system as claimed in claim 10, wherein said second means comprises a division circuit, responsive to an adding result, for performing a predetermined dividing calculation on said adding result and for generating quotient and remainder outputs resulting from the calculation, and an adder, coupled to said first means and said division circuit for adding the remainder output to the counting value supplied from said first means, said adder generating the adding result, the quotient output of said division circuit being used as the stuffing information.