Scanning circuit for pressure responsive array
First Claim
1. A circuit for scanning an array of pressure responsive sensor points, each of said points being intersected by one of a plurality of first electrodes and one of a plurality of second electrodes, there being a pressure sensitive resistance between the electrodes intersecting at each of said points, the circuit comprising:
- means for generating a test signal;
a first multiplexer for selectively applying the test signal to each first electrode, the test signal flowing through the pressure sensitive resistance for sensor points intersected by said first electrode for which the resistance is in a lowered resistance state to the second electrode intersecting the point;
an output circuit; and
a second multiplexer for selectively passing test signals appearing on the second electrodes to the output circuit;
said output circuit including a means for controlling the sensitivity of the circuit.
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Accused Products
Abstract
A scanning circuit for an array of pressure responsive sensor points which permits the sensitivity of the circuit to be controlled. In particular, the sensitivity of the circuit may be controlled by controlling a test and/or reference voltage used with the circuit and different sensitivity or resolutions may be provided for different areas of the array. The circuit also provides enhanced interelectrode isolation, permitting a single test voltage to be utilized to scan all sensor points on a given input electrode and further reduces the time required to scan the array by reducing trace capacitance discharge time and by inhibiting processing for sensor points which are not of interest. The accuracy of pressures being sensed is also enhanced by adjusting the test voltage to compensate for load variations.
230 Citations
17 Claims
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1. A circuit for scanning an array of pressure responsive sensor points, each of said points being intersected by one of a plurality of first electrodes and one of a plurality of second electrodes, there being a pressure sensitive resistance between the electrodes intersecting at each of said points, the circuit comprising:
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means for generating a test signal; a first multiplexer for selectively applying the test signal to each first electrode, the test signal flowing through the pressure sensitive resistance for sensor points intersected by said first electrode for which the resistance is in a lowered resistance state to the second electrode intersecting the point; an output circuit; and a second multiplexer for selectively passing test signals appearing on the second electrodes to the output circuit; said output circuit including a means for controlling the sensitivity of the circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A circuit for scanning an array of pressure responsive sensor points, each of said points being intersected by one of a plurality of first electrodes and one of a plurality of second electrodes, there being a pressure sensitive resistance between the electrodes intersecting at each of said points, the circuit comprising:
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means for generating a test voltage; a first multiplexer for selectively applying the test voltage to each first electrode, the test voltage flowing through the pressure sensitive resistance for sensor points intersected by said first electrode for which the resistance is in a lowered resistance state to the second electrode intersecting the point; an output circuit and means for sensing the load to which said test voltage is being applied, said means including means for sensing the current for said test voltage; means responsive to the sensed current for controlling the value of the test voltage, said means including an A/D converter for converting the sensed current to a digital value, a digital processor for generating a new digital test voltage value in response to the sensed current, a D/A converter for generating a new test voltage value in response to the digital test voltage value, and means for utilizing the new test voltage value to produce the test voltage; and a second multiplexer for selectively passing test voltages appearing on the second electrodes to the output circuit.
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Specification