Fabrication process for multilevel interconnections in a semiconductor device

• US 5,506,177 A
• Filed: 02/24/1995
• Issued: 04/09/1996
• Est. Priority Date: 02/28/1994
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Homma, Tetsuya, Kishimoto, Koji
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): EVERHART, CARIDAD
• Application Number:
  US08/394,943
• Time in Patent Office: 410 Days
• Field of Search: 437/195, 437/231, 437/982, 437/228 G, 148/DIG. 133
• US Class Current: 438/624
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76828 thermal treatment
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence

Abstract

After forming lower level wiring and plasma oxide layer, SOG film is applied by applying a solution containing hydrogen silsesquioxane as primary component under rotation. Pre-baking of the SOG film is performed by a first heat treatment and causes reflow thereof by a second heat treatment at a temperature higher than the first heat treatment. Subsequently, another plasma oxide layer is formed. By this, in an interlayer insulation layer including SOG film, occurrence of crack and so forth can be prevented and water resistance can be improved.

Claims

1. A fabrication process for a semiconductor device comprising the steps of:

forming a plurality of lower level wiring, disposing insulation layer therebetween, on the surface of a silicon substrate;

forming a first silicon oxide layer covering the surfaces of said lower level wiring and the surface of said insulation layer by a first plasma chemical vapor deposition method;

forming an inorganic SOG film containing Si--H coupling and covering said first silicon oxide layer by applying a solution containing hydrogenated silsesquioxane ((HSiO_3/2)_n) as a primary component and pre-baking by a first thermal process;

performing reflow of said SOG film by a second thermal process at a temperature higher than that of said first thermal process;

forming a second silicon oxide layer covering the surface of reflown SOG film by a second plasma chemical vapor deposition; and

forming an upper level wiring over said second silicon oxide layer.

2. A fabrication process for a semiconductor device as set forth in claim 1, wherein said lower level wiring is a film selected from a group of aluminum or aluminum alloy film, copper or copper alloy film, gold or gold alloy film and stacked film of at least one of the films and other film.

3. A fabrication process for a semiconductor device as set forth in claim 1, which further comprises a step of flattening said reflown SOG film by chemical mechanical polishing method.

4. A fabrication process for a semiconductor device as set forth in claim 1, wherein at least one of said first plasma chemical vapor deposition method and said second plasma chemical vapor deposition method is a plasma chemical vapor deposition employing tetraethylorthosilicate and oxygen as materials.

5. A fabrication process for a semiconductor device as set forth in claim 1, wherein at least one of said first plasma chemical vapor deposition method and said second plasma chemical vapor deposition method is a plasma chemical vapor deposition employing silane and nitrogen monoxide as materials.

6. A fabrication process for a semiconductor device comprising the steps of:

forming a plurality of lower level wiring, disposing insulation layer therebetween, on the surface of a silicon substrate;

forming a first silicon oxide layer covering the surfaces of said lower level wiring and the surface of said insulation layer by a first plasma chemical vapor deposition method;

forming an inorganic SOG film containing Si--H coupling and covering said first silicon oxide layer by applying a solution containing hydrogenated silsesquioxane ((HSiO_3/2)_n) as a primary component and pre-baking by a first thermal process;

performing reflow of said SOG film by a second thermal process at a temperature higher than that of said first thermal process;

performing oxygen plasma process for the surface of the reflown SOG film;

solidifying said SOG film processed by oxygen plasma process by a third thermal process at a temperature higher than said first thermal process;

forming a second silicon oxide layer covering the surface of reflown SOG film by a second plasma chemical vapor deposition; and

forming upper level wiring over said second silicon oxide layer.

7. A fabrication process for a semiconductor device as set forth in claim 6, wherein said lower level wiring is a film selected from a group of aluminum or aluminum alloy film, copper or copper alloy film, gold or gold alloy film and stacked film of at least one of the films and other film.

8. A fabrication process for a semiconductor device as set forth in claim 6, which further comprises a step of flattening said reflown SOG film by chemical mechanical polishing method.

9. A fabrication process for a semiconductor device as set forth in claim 6, wherein at least one of said first plasma chemical vapor deposition method and said second plasma chemical vapor deposition method is a plasma chemical vapor deposition employing tetraethylorthosilicate and oxygen as materials.

10. A fabrication process for a semiconductor device as set forth in claim 6, wherein at least one of said first plasma chemical vapor deposition method and said second plasma chemical vapor deposition method is a plasma chemical vapor deposition employing silane and nitrogen monoxide as materials.