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Fabrication process for multilevel interconnections in a semiconductor device

  • US 5,506,177 A
  • Filed: 02/24/1995
  • Issued: 04/09/1996
  • Est. Priority Date: 02/28/1994
  • Status: Expired due to Term
First Claim
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1. A fabrication process for a semiconductor device comprising the steps of:

  • forming a plurality of lower level wiring, disposing insulation layer therebetween, on the surface of a silicon substrate;

    forming a first silicon oxide layer covering the surfaces of said lower level wiring and the surface of said insulation layer by a first plasma chemical vapor deposition method;

    forming an inorganic SOG film containing Si--H coupling and covering said first silicon oxide layer by applying a solution containing hydrogenated silsesquioxane ((HSiO3/2)n) as a primary component and pre-baking by a first thermal process;

    performing reflow of said SOG film by a second thermal process at a temperature higher than that of said first thermal process;

    forming a second silicon oxide layer covering the surface of reflown SOG film by a second plasma chemical vapor deposition; and

    forming an upper level wiring over said second silicon oxide layer.

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