Microcomputer for IC card

• US 5,506,396 A
• Filed: 02/08/1994
• Issued: 04/09/1996
• Est. Priority Date: 02/09/1993
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Asami, Kazuo
• Primary Examiner(s): Hajec, Donald T.
• Assistant Examiner(s): FILIPEK, JEFFER
• Application Number:
  US08/193,460
• Time in Patent Office: 791 Days
• Field of Search: 235/492, 235/487, 364/DIG. 2, 364/938, 364/938.1, 364/938.2, 364/938.3, 364/938.4, 380/25, 380/49, 380/50, 902/1, 902/26
• US Class Current: 235/492
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: G06F 11/24 Marginal checking or other specified testing methods not covered by G06F11/26, e.g. race tests
• CPC Class Codes: G06F 12/1433 for a module or a part of a module
• CPC Class Codes: G06Q 20/3558 Preliminary personalisation for transfer to user
• CPC Class Codes: G07F 7/1008 Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system

Abstract

A microcomputer for an IC card arranged so that only a user mode can be performed after the microcomputer has been shipped to a user. Data representing that the microcomputer has been shipped is written at the time of shipment in a test region of an EEPROM. A shipment confirmation routine for confirming whether the shipment data has been written is performed before execution of a branch routine for branching to other programs in accordance with an executed command supplied from outside the microcomputer. If the shipment data has been written in the test region of the EEPROM as confirmed in the shipment confirmation routine, only branching to the user mode is permitted.

Claims

1. A microcomputer for an IC card comprising:

a mask ROM storing a user program, a test program, and a branch routine for selectively branching to the user and test programs in accordance with an execution command;

a CPU for processing data in accordance with the branch routine and the user and test programs stored in said mask ROM;

a RAM for temporarily storing data;

an EEPROM for storing data, having a plurality of memory locations, and including designated memory locations forming a test EEPROM region that cannot be accessed from the user program;

an input/output control circuit for controlling input of data to and output of data from said microcomputer;

terminals for establishing external electrical connections to said microcomputer; and

a bus mutually connecting said mask ROM, said CPU, said RAM, said EEPROM, and said input/output circuit, wherein said mask ROM includes a shipment confirmation routine performed before the branch routine is performed, said test EEPROM region includes memory locations where shipment data representing whether said microcomputer has been shipped is written, and branching to the user program takes place without exception if confirmation has been made in the shipment confirmation routine that the shipment data has been written in the test EEPROM region.

2. The microcomputer for an IC card of claim 1 wherein said mask ROM stores a password confirmation routine, and wherein, if the shipment confirmation routine confirms that the shipment data has not been written, branching to the test program only occurs if the password confirmation routine determines that a valid password has been input through said input/output control circuit.

3. A microcomputer for an IC card comprising:

a mask ROM storing a user program, a test program, and a branch routine for selectively branching to the user and test programs in accordance with an execution command;

a CPU for processing data in accordance with the branch routine and the user and test programs stored in said mask ROM;

a RAM for temporarily storing data;

an EEPROM for storing data, having a plurality of memory locations, and including designated memory locations forming a test EEPROM region that cannot be accessed from the user program;

an input/output control circuit for controlling input of data to and output of data from said microcomputer;

terminals for establishing external electrical connections to said microcomputer; and

a bus mutually connecting said mask ROM, said CPU, said RAM, said EEPROM, and said input/output circuit, wherein said terminals include a power source terminal;

voltage detection means for detecting whether a power supply voltage at said power source terminal has decreased, said mask ROM including, before the branch routine, a shipment confirmation routine and a voltage detection routine for detecting the power supply voltage at said power source terminal regardless of whether the shipment confirmation routine has been performed, said test EEPROM region includes a region in which shipment data representing that said microcomputer has been shipped is written, and branching to the user program takes place without exception when a decrease in the power supply voltage at said power source terminal has been detected in the voltage detection routine even if the shipment data has not been written in said test EEPROM region as determined in said shipment confirmation routine.

4. A microcomputer for an IC card comprising:

a mask ROM storing a user program, a test program, a burn-in test program, and a branch routine for selectively branching to the user, test, and burn-in test programs in accordance with an execution command;

a CPU for processing data in accordance with the branch routine and the user, test, and burn-in test programs stored in said mask ROM;

a RAM for temporarily storing data;

an EEPROM for storing data, having a plurality of memory locations, and including designated memory locations forming a test EEPROM region that cannot be accessed from the user program;

an input/output control circuit for controlling input of data to and output of data from said microcomputer;

terminals for establishing external electrical connections to said microcomputer; and

a bus mutually connecting said mask ROM, said CPU, said RAM, said EEPROM, and said input/output circuit, wherein said mask ROM includes a burn-in data confirmation routine performed before branching to the burn-in test program takes place, said test EEPROM region includes memory locations where burn-in data indicating that the burn-in test program has been executed is written, and stopping operation of the microcomputer, without exception, if the burn-in data confirmation routine determines that the burn-in data has not been written in said test EEPROM region.