Semiconductor integrated circuit device having an improved packaging structure

• US 5,506,448 A
• Filed: 12/22/1994
• Issued: 04/09/1996
• Est. Priority Date: 12/27/1993
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Morishige, Sueo
• Primary Examiner(s): Mintel, William
• Assistant Examiner(s): POTTER, ROY KARL
• Application Number:
  US08/361,970
• Time in Patent Office: 474 Days
• Field of Search: 257/697, 257/704, 257/723, 257/705, 257/701, 257/700, 257/778, 257/782
• US Class Current: 257/697
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/0105 Tin [Sn]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15153 the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 Monolayer substrate
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15312 being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/1532 the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]

Abstract

Semiconductor IC device comprises an IC chip fixed to a top surface of a carrier board having top electrodes located on a periphery of the top surface. The carrier board further includes bottom electrodes on a bottom surface each connected to corresponding one of the top electrodes by an interconnection formed within the carrier board. The bottom electrodes of the carrier board are electrically connected to and mechanically fixed to internal electrodes of a package container having pin grids each connected to corresponding one of the internal electrodes. The bottom electrodes are arranged in a matrix for standardized structure. Variety of types of inexpensive carrier boards are prepared to variety of IC chips so that the number of the types of expensive package containers is reduced and a stock cost thereof is significantly reduced.

Claims

1. A semiconductor integrated circuit comprising:

at least one IC chip including therein a plurality of semiconductor elements and a plurality of bonding pads connected to said semiconductor elements;

a carrier board having a top surface for mounting thereon a plurality of top electrodes, at least a part of said top electrodes being connected to a corresponding one of said bonding pads by a bonding wire, said carrier board further having a bottom surface for mounting thereon a plurality of bottom electrodes arranged in a matrix, and first interconnections formed within said carrier board and connecting each of said top electrodes with each corresponding one of said bottom electrodes, said IC chip being fixed to said top surface; and

a package container having an internal surface for mounting a plurality of internal electrodes arranged in correspondence to said bottom electrodes, an external surface for mounting a plurality of external electrodes, and second interconnections connecting each of said internal electrodes to each corresponding one of said external electrodes, said carrier board being fixed to said package container through bonding each of said bottom electrodes to each corresponding one of said internal electrodes.

2. A semiconductor integrated circuit as defined in claim 1 wherein said top electrodes are arranged in at least one row on said top surface.

3. A semiconductor integrated circuit as defined in claim 1 wherein said bonding wire is metallic capillary wire.

4. A semiconductor integrated circuit as defined in claim 1 wherein said carrier board includes a laminate of a plurality of resin layers.

5. A semiconductor integrated circuit as defined in claim 1 wherein said carrier board includes a laminate of a plurality of ceramic layers.

6. A semiconductor integrated circuit as defined in claim 1 further comprising a cap encapsulating said IC chip and said carrier board together with said package container.

7. A semiconductor integrated circuit as defined in claim 1 wherein each of said bottom electrodes is bonded to each corresponding internal electrode by a soldering material.

8. A semiconductor integrated circuit as defined in claim 1 wherein each of said bottom electrodes is bonded to each corresponding internal electrode by a conductive resin.

9. A semiconductor integrated circuit as defined in claim 1 wherein said IC chip is die-bonded to said top surface of said carrier board.

10. A semiconductor integrated circuit comprising:

a plurality of IC chips each including a plurality of semiconductor elements and a plurality of bonding pads connected to said semiconductor elements;

a plurality of carrier boards each positioned for mounting a corresponding one of said IC chips thereon, each of said carrier boards having a top surface for mounting a plurality of top electrodes and a corresponding one of said IC chips, at least a part of said top electrodes being connected to a corresponding one of said bonding pads by a bonding wire, each carrier board further having a bottom surface for mounting a plurality of bottom electrodes arranged in a matrix, and first interconnections formed within said carrier board and connecting each of said top electrodes with each corresponding one of said bottom electrodes; and

a package container having a plurality of recesses each for receiving a corresponding one of said carrier boards, each of said recesses being provided with a plurality of internal electrodes arranged correspondingly to said bottom electrodes, said package container having an external surface for mounting thereon a plurality of external electrodes, and second interconnections connecting each of said internal electrodes to each corresponding one of said external electrodes, each of said carrier boards being fixed to said package container through bonding each of said bottom electrodes to each corresponding one of said internal electrodes.

11. A semiconductor integrated circuit comprising:

at least one IC chip including therein a plurality of semiconductor elements and a plurality of bonding pads connected to said semiconductor elements;

a carrier board having a top surface for mounting thereon said IC chip and a plurality of top electrodes, at least a part of said top electrodes being connected to a corresponding one of said bonding pads by a bonding wire, said carrier board having a bottom surface for mounting thereon a plurality of bottom electrodes arranged in a matrix, and first interconnections formed within said carrier board and connecting each of said top electrodes with each corresponding one of said bottom electrodes; and

a package container having a top surface having a plurality of external electrodes, a bottom surface implementing a radiator, an inner surface disposed opposite to said bottom surface and mounting a plurality of internal electrodes arranged correspondingly to said bottom electrodes, and second interconnections connecting each of said internal electrodes to each corresponding one of said external electrodes, said carrier board being fixed to said inner surface of said package container through bonding each of said bottom electrodes to each corresponding one of said internal electrodes.