Flip-chip semiconductor devise having an electrode pad covered with non-metal member

• US 5,506,451 A
• Filed: 12/23/1994
• Issued: 04/09/1996
• Est. Priority Date: 12/27/1993
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hyugaji, Masahiko
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US08/363,322
• Time in Patent Office: 473 Days
• Field of Search: 257/744, 257/745, 257/763, 257/766, 257/778, 257/777, 257/779, 257/764, 257/432, 257/459, 257/81, 257/447, 257/448, 257/772, 257/758
• US Class Current: 257/778
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05169 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/0103 Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01045 : Rhodium [Rh]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/10336 : Aluminium gallium arsenide [AlGaAs]
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12043 : Photo diode
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13063 : Metal-Semiconductor Field-Effect Transistor [MESFET]
• CPC Class Codes: H01L 2924/13064 : High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 31/02161 : for devices characterised by at least one potential jump barrier or surface barrier
• CPC Class Codes: H01L 31/02325 : the optical elements not being integrated nor being directly associated with the device

Abstract

An N-InP buffer layer is deposited on an N⁺ -InP substrate, an InGaAs light-absorbing layer is deposited on the buffer layer, an N^- -InP cap layer is deposited on the light-absorbing layer, and a P-type impurity region is formed in the light-absorbing layer and the cap layer. Next, a masking film is formed on the cap layer, and with this masking film serving as a mask, the cap layer, the light-absorbing layer, the buffer layer are etched, thus forming a P-type electrode forming region and an N-type electrode forming region. Next, an insulating film is provided for the periphery portion of the P-type impurity region of the cap layer. Electrode pads having a laminated structure is formed respectively on the P-type and N-type electrode forming regions, and a non-metal member is formed on the insulating film and on the surface, the periphery and the side surface of the electrode pad of the P-type electrode.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having an electrode forming region provided thereon, said electrode forming region including an impurity region;

an insulating film provided on said electrode forming region, said insulating film having an opening exposing said impurity region;

an electrode pad provided on said insulating film, said electrode pad being in contact with said impurity region through said opening of said insulating film; and

a non-metal member provided on a surface and a side surface of said electrode pad, said non-metal member having an opening exposing said surface of said electrode pad,

wherein said non-metal member prevents a metal component contained in a solder provided on said surface of said electrode pad from diffusing into said impurity region through the opening of said insulating film.

2. A semiconductor device according to claim 1, wherein said non-metal member is made of one of silicon oxide, silicon nitride and polyimide.

3. A semiconductor device according to claim 2, wherein said electrode pad includes a metal layer made of at least Ni, Pd, Pt, Rh and Ti.

4. A semiconductor device according to claim 3, wherein said electrode pad is made of one of a single and a plurality of metal layers.

5. A semiconductor device according to claim 4, wherein said solder mainly contains one of the group consisting of at least Au, Sn, Pb and In.

16. A semiconductor device according to claim 1, wherein said electrode forming region includes a buffer layer, light absorbing layer and cap layer, said impurity region being located in said cap layer and said light-absorbing layer.

17. A semiconductor device according to claim 1, wherein said non-metal member prevents at least one of Au, Sn, Pb, and In contained in said solder from diffusing into said impurity region.

18. A semiconductor device according to claim 1, wherein said impurity region and said electrode forming region are a p-type.

19. A semiconductor device according to claim 18, and further comprising:

n-type electrode forming regions arranged at both sides of said p-type electrode forming regions.

20. A semiconductor device according to claim 19, wherein said non-metal member being provided on only said p-type electrode forming region.

6. A semiconductor device comprising:

a semiconductor substrate having an electrode forming region provided thereon, said electrode forming region including an impurity region;

an insulating film provided on said electrode forming region, said insulating film having an opening exposing said impurity region;

an electrode pad provided on said insulating film, said electrode pad being in contact with said impurity region through said opening of said insulating film;

a non-metal member provided on a surface and a side surface of said electrode pad, said non-metal member having an opening exposing said surface of said electrode pad; and

a solder bump provided on said surface of said electrode pad though the opening of said non-metal member,

wherein said non-metal member prevents a metal component contained in said solder bump from diffusing into said impurity region.

7. A semiconductor device according to claim 6, wherein said non-metal member is made of one of silicon oxide, silicon nitride and polyimide.

8. A semiconductor device according to claim 6, wherein said electrode pad includes a metal layer made of at least Ni, Pd, Pt, Rh and Ti.

9. A semiconductor device according to claim 6, wherein said electrode pad is made of one of a single and a plurality of metal layers.

10. A semiconductor device according to claim 6, wherein said solder bump mainly contains one of the group consisting of at least Au, Sn, Pb and In.

21. A semiconductor device according to claim 6, wherein said electrode forming region includes a buffer layer, light absorbing layer and cap layer, said impurity region being located in said cap layer and said light-absorbing layer.

22. A semiconductor device according to claim 6, wherein said non-metal member prevents at least one of Au, Sn, Pb, and In contained in said solder from diffusing into said impurity region.

23. A semiconductor device according to claim 6, wherein said impurity region and said electrode forming region are a p-type.

24. A semiconductor device according to claim 23, and further comprising:

n-type electrode forming regions arranged at both sides of said p-type electrode forming regions.

25. A semiconductor device according to claim 24, wherein said non-metal member being provided on only said p-type electrode forming region.

11. A semiconductor device comprising:

a semiconductor substrate having an electrode forming region provided thereon, said electrode forming region including an impurity region;

an insulating film provided on said electrode forming region, said insulating film having an opening exposing said impurity region;

an electrode pad provided on said insulating film, said electrode pad being in contact with said impurity region through said opening of said insulating film;

a non-metal member provided on a surface and a side surface of said electrode pad, said non-metal member having an opening exposing said surface of said electrode pad; and

a mounting member for mounting said semiconductor substrate with solder by using said surface of said electrode pad as a contact surface,

wherein said non-metal member prevents a metal component contained in a solder provided on said surface of said electrode pad from diffusing into said impurity region through the opening of said insulating film.

12. A semiconductor device according to claim 11, wherein said non-metal member is made of one of silicon oxide, silicon nitride and polyimide.

13. A semiconductor device according to claim 12, wherein said electrode pad includes a metal layer made of at least Ni, Pd, Pt, Ph and Ti.

14. A semiconductor device according to claim 13, wherein said electrode pad is made of one of a single and a plurality of metal layers.

15. A semiconductor device according to claim 14, wherein said solder mainly contains one of the group consisting of at least Au, Sn, Pb and In.

26. A semiconductor device according to claim 11, wherein said electrode forming region includes a buffer layer, light absorbing layer and cap layer, said impurity region being located in said cap layer and said light-absorbing layer.

27. A semiconductor device according to claim 11, wherein said non-metal member prevents at least one of Au, Sn, Pb, and In contained in said solder from diffusing into said impurity region.

28. A semiconductor device according to claim 11, wherein said impurity region and said electrode forming region are a p-type.

29. A semiconductor device according to claim 28, and further comprising:

n-type electrode forming regions arranged at both sides of said p-type electrode forming regions.

30. A semiconductor device according to claim 29, wherein said non-metal member being provided on only said p-type electrode forming region.