Tamper detectable electronic security package

• US 5,506,566 A
• Filed: 05/06/1993
• Issued: 04/09/1996
• Est. Priority Date: 05/06/1993
• Status: Expired due to Fees

• Current Assignee: Nortel Networks Limited (Nortel Networks Corporation)
• Original Assignee: Northern Telecom Limited (Nortel Networks Corporation)
• Inventors: Oldfield, John A., Sabry, H. Charles, Jones, Adrian D.
• Primary Examiner(s): MULLEN, THOMAS J
• Application Number:
  US08/057,390
• Time in Patent Office: 1,069 Days
• Field of Search: 340/550, 340/566, 340/658, 340/522-554, 340/508, 109/41-42, 206/459.1, 206/807, 361/399, 361/415, 361/748
• US Class Current: 340/550
• CPC Class Codes: G08B 13/128 the housing being an electronic circuit unit, e.g. memory or CPU chip protecting computer components in secure or tamper resistant housings G06F21/86; protecting computer input devices, e.g. keyboards G06F21/83

Abstract

An intrusion detection electronic circuit package, includes a containment wall in combination with first and second transmission lines being organized in patterns spaced adjacent one another. Electronic circuitry, residing within the containment wall, includes a transmitter for transmitting signals in anti-phase relationship via the first and second transmission lines respectively. A receiver receives signals from the transmission lines and a detector connected to the receiver uses EXCLUSIVE OR logic to detect any significant in-phase components or interruptions in the signals received at the first and second inputs of the receiver. Disturbance of either transmission line in any attempt to breach the containment wall is likely to be detected.

Claims

1. An intrusion detection electronic circuit comprising:

a containment wall in combination with first and second transmission lines, the first and second transmission lines being spaced adjacent one another throughout the containment wall;

a transmitter having first and second outputs connected to the first and second transmission lines respectively, for transmitting signals in antiphase relationship one with the other;

a receiver including first and second inputs, connected to the first and second transmission lines respectively for receiving signals therefrom; and

a detector, for detecting an in phase component in signals received at the first and second inputs.

2. An intrusion detection electronic circuit as defined in claim 1, wherein the first and second transmission lines are arranged with the first-overlying the second.

3. An intrusion detection electronic circuit as defined in claim 1, wherein the first and second transmission lines are arranged in combination to resemble a screen.

4. An intrusion detection electronic circuit as defined in claim 1, wherein portions of the first and second transmission lines are arranged substantially in parallel one with the other.

5. An intrusion detection electronic circuit as defined in claim 1, wherein portions of the first and second transmission lines are arranged substantially in parallel one with the other in a zigzag pattern.

6. An intrusion detection electronic circuit as defined in claim 1, wherein the containment wall contains a plurality of layers of the transmission lines.

7. An intrusion detection electronic circuit as defined in claim 1, wherein the containment wall comprises an electrically insulating material and each transmission line consists of an electrically conductive path carried by the containment wall.

8. An intrusion detection electronic circuit as defined in claim 1, wherein a cavity is defined within a plurality of the containment walls.

9. An intrusion detection electronic circuit as defined in claim 8, wherein the cavity contains said transmitter, said receiver and said detector.

10. An intrusion detection electronic circuit as defined in claim 1, wherein the transmitter includes a square wave generator and a digital driver circuit connected to the first and second outputs and being responsive to signals from the square wave generator for providing signals in antiphase relationship at the first and second outputs.

11. An intrusion detection electronic circuit as defined in claim 1, wherein the receiver includes first and second voltage dividers having first and second voltage taps capacitively connected to the first and second inputs in common with inputs of first and second amplifiers respectively, the first amplifier for generating amplitude limited signals in response to signals appearing at the first voltage tap, and the second amplifier for generating amplitude limited signals in response to signals appearing at the second voltage tap.

12. An intrusion detection circuit as defined in claim 11, wherein the first and second amplifiers are Schmitt amplifiers.

13. An intrusion detection electronic circuit as defined in claim 11, wherein the detector includes an EXCLUSIVE OR logic circuit having an output coupled to a latch circuit, the EXCLUSIVE OR logic circuit being responsive to any antiphase asymmetry in the limited signals by asserting a signal for setting the latch circuit.

14. An intrusion detection electronic circuit comprising:

a containment wall of electrically insulating material in combination with first and second transmission lines, the transmission lines consisting of first and second electrically conductive paths, respectively, carried by the containment wall, the first and second conductive paths being arranged adjacent one another to resemble a screen;

a square wave generator and a driver circuit being responsive to signals from the square wave generator for transmitting first and second signals in antiphase relationship through the first and second transmission lines, respectively;

an EXCLUSIVE OR logic circuit having inputs coupled to receive signals from the transmission lines and an output coupled to a latch circuit, the EXCLUSIVE OR logic circuit being responsive to any antiphase asymmetry in the signals from the transmission lines by asserting a signal for setting the latch circuit.

15. An intrusion detection electronic circuit comprising:

a containment wall of electrically insulating material in combination with first and second transmission lines, the first and second transmission lines including first and second electrically conductive paths respectively, being carried adjacent one another by the containment wall;

an oscillator for generating pulse signals at a fundamental frequency within an audible spectrum of frequencies;

a driver circuit means being responsive to the pulse signals for transmitting first and second signals in antiphase relationship through the first and second transmission lines, respectively;

first and second terminating means connected to the first and second transmission lines remote from the driver circuit means;

first and second amplifiers having inputs connected with the first and second terminating means respectively, the first amplifier for generating amplitude limited signals in response to signals appearing at the first terminating means, and the second amplifier for generating amplitude limited signals in response to signals appearing at the second terminating means;

a latch means being responsive to an occurrence of a set signal to be in a set state, and in the absence of a set signal being responsive to an occurrence of a clear signal to be in an alternate state;

an EXCLUSIVE OR logic circuit having inputs coupled to receive signals from the first and second amplifiers, and an output, the EXCLUSIVE OR logic circuit being responsive to any antiphase asymmetry in the limited signals by asserting the set signal at its output; and

a low pass filter means connected between the output of the EXCLUSIVE OR logic circuit and an input of the latch means.

16. An intrusion detection electronic circuit comprising:

a containment wall of electrically insulating material in combination with first and second transmission lines, the first and second transmission lines including first and second electrically conductive paths, respectively, being carried adjacent one another by the containment wall;

an oscillator for generating pulse signals at a fundamental frequency within an audible spectrum of frequencies;

a driver circuit means being responsive to the pulse signals for transmitting first and second signals in antiphase relationship through the first and second transmission lines, respectively;

first and second terminating means connected to the first and second transmission lines remote from the driver circuit means;

first and second amplifiers having inputs connected with the first and second terminating means respectively, the first and second amplifiers for generating amplitude limited signals in response to signals at the first and second terminating means;

a latch means being responsive to an occurrence of a set signal to be in a set state, and in the absence of a set signal being responsive to an occurrence of a clear signal to be in an alternate state;

an EXCLUSIVE OR logic circuit having inputs coupled to receive signals from the first and second amplifiers, and an output, the EXCLUSIVE OR logic circuit being responsive to any antiphase asymmetry in the amplitude limited signals by asserting the set signal at its output; and

a blanking means for negating each assertion of the set signal for a predetermined duration of time.

17. A method for detecting an incidence of tampering at a barrier which includes a pair of electrical conductors extending throughout the barrier, the method comprising the steps of:

a) transmitting first and second electrical signals in a symmetrical antiphase relationship from a first position through respective ones of the pair of electrical conductors;

b) at a second position remote from the first position along the pair of electrical conductors detecting a phase relationship between said first and second electrical signals which is other than an antiphase relationship; and

c) in response to a detecting occurrence in step b) extending beyond a predetermined period of time, latching a tamper signal as an indication of tampering.

18. A method for detecting an incidence of intrusion as defined in claim 17, wherein the signals transmitted in symmetrical antiphase relationship are square waves and the wherein step b)is performed by EXCLUSIVE ORING said first and second electrical signals.