Dynamic memory with isolated digit lines
First Claim
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1. A memory responsive to a data signal, an address signal, and a write control signal, the memory comprising:
- a. a cell for storing data conveyed by the data signal;
b. a cell selection circuit coupled to the address signal for providing a row signal and a column signal;
c. a digit line;
d. an access circuit for coupling the cell to the digit line in response to the row signal;
e. a timing circuit responsive to the write control signal, for providing a first timing signal and a second timing signal;
f. a sense amplifier comprising a sense node, the sense amplifier coupled to the cell selection circuit, the sense amplifier for establishing, on the sense node a signal conveying stored data;
g. an isolator coupled to the timing circuit and responsive to the first timing signal, the isolator coupled between the digit line and the sense node for isolating the digit line from the sense node; and
h. a buffer coupled to the digit line for driving the data signal onto the digit line;
wherein the timing circuit is responsive to the write control signal for providing the first timing signal to isolate the cell from the sense node while the data signal is coupled to the sense node for a time at least sufficient for the sense amplifier to attain a state corresponding to the data signal, then for providing the second tirning signal to isolate the buffer from the sense node while the sense amplifier is coupled to the cell for a time at least sufficient for the cell to attain a state corresponding to the sense amplifier.
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Abstract
A memory in which a portion of a digit line is isolated from the remainder of the digit line during a write cycle has improved performance. In the conventional architecture of a memory device, cells are arranged in rows and columns and a sense amplifier is employed for a pair of columns, located between a pair of complementary digit lines. An embodiment of the present invention in this architecture provides improved means for isolating the sense amplifier during a write cycle.
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Citations
31 Claims
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1. A memory responsive to a data signal, an address signal, and a write control signal, the memory comprising:
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a. a cell for storing data conveyed by the data signal; b. a cell selection circuit coupled to the address signal for providing a row signal and a column signal; c. a digit line; d. an access circuit for coupling the cell to the digit line in response to the row signal; e. a timing circuit responsive to the write control signal, for providing a first timing signal and a second timing signal; f. a sense amplifier comprising a sense node, the sense amplifier coupled to the cell selection circuit, the sense amplifier for establishing, on the sense node a signal conveying stored data; g. an isolator coupled to the timing circuit and responsive to the first timing signal, the isolator coupled between the digit line and the sense node for isolating the digit line from the sense node; and h. a buffer coupled to the digit line for driving the data signal onto the digit line; wherein the timing circuit is responsive to the write control signal for providing the first timing signal to isolate the cell from the sense node while the data signal is coupled to the sense node for a time at least sufficient for the sense amplifier to attain a state corresponding to the data signal, then for providing the second tirning signal to isolate the buffer from the sense node while the sense amplifier is coupled to the cell for a time at least sufficient for the cell to attain a state corresponding to the sense amplifier. - View Dependent Claims (2)
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3. A dynamic memory responsive to a data signal, the memory comprising:
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a. a first conductor and a second conductor, the first conductor having a capacitance, the capacitance having a charge; b. a sense amplifier coupled to the first conductor; c. a first switch for coupling the data signal to the first conductor so that the charge and the sense amplifier are responsive to the data signal while the first switch is closed; d. a second switch in series between the first conductor and the second conductor; e. a dynamic memory cell coupled to the second conductor; and f. a timing circuit for operating the first switch and the second switch so that after the sense amplifier and the capacitance have responded to the data signal, the first switch is opened and the second switch is closed, thereby writing data to the cell. - View Dependent Claims (4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A dynamic memory responsive to a data signal, the memory comprising:
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a. a first, a second, and a third conductor, the first conductor having a capacitance, the capacitance having a charge; b. a sense amplifier coupled to the second conductor; c. a first switch for coupling the data signal to the first conductor; d. a second switch in series between the first conductor and the second conductor, so that the charge and the sense amplifier are responsive to the data signal while the first switch and the second switch are closed; e. a third switch in series between the second conductor and the third conductor; f. a first dynamic memory cell coupled to the third conductor; and g. a timing circuit for operating the first, the second, and the third switch so that after the sense amplifier and the capacitance have responded to the data signal, the first switch is opened and the third switch is closed, thereby writing data to the first cell. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
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Specification