Analog-digital mixed master including therein a test circuit

• US 5,506,851 A
• Filed: 06/05/1995
• Issued: 04/09/1996
• Est. Priority Date: 03/30/1992
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Fuse, Mamoru
• Primary Examiner(s): Voeltz, Emanuel T.
• Assistant Examiner(s): Stamber, Eric W.
• Application Number:
  US08/461,542
• Time in Patent Office: 309 Days
• Field of Search: 371/22.1, 371/22.3, 371/22.5, 371/22.6, 364/488, 364/489, 364/490, 364/578, 324/158.1, 324/73.1
• US Class Current: 714/724
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/3167 Testing of combined analog and digital circuits testing ADC's H03M1/1071
• CPC Class Codes: G06F 11/2733 Test interface between tester and unit under test

Abstract

In an analog-digital mixed master for a Bi-CMOS analog/digital mixed LSI, an analog circuit and a digital circuit are interconnected through selectors, which are also connected to test terminals and which are controlled by test mode terminals. By changing the signals applied to the test mode terminals, the analog circuit and the digital circuit are interconnected through the selectors, or the analog circuit is connected through the selectors to the test terminals, or the digital circuit is connected through the selectors to the test terminals. Thus, the analog circuit and the digital circuit can be tested independently of each other.

Claims

1. A semiconductor integrated circuit comprising:

an analog circuit for processing input signals supplied thereto and for producing at least one first output signal;

a digital circuit for processing input signals supplied thereto and for producing at least one second output signal;

a first signal line, coupled between said analog circuit and said digital circuit, for transferring said first output signal to said digital circuit;

a second signal line, coupled between said digital circuit and said analog circuit, for transferring said second output signal to said analog circuit;

a first test mode terminal supplied with a first test mode signal, said first test mode signal taking one of an active level and an inactive level in accordance with operation modes;

a second test mode terminal supplied with a second test mode signal, said second test mode signal taking one of an active level and an inactive level in accordance with operation modes;

a first test signal input/output terminal;

a second test signal input/output terminal;

a first selector, inserted in said first signal line, for dividing said first signal line into first and second partial signal lines and coupled to said first and second test mode terminals and said first test signal input/output terminal; and

a second selector, inserted in said second signal line, for dividing said second signal line into third and fourth partial signal lines and coupled to said first and second test mode terminals and said second test signal input/output terminal,

said first selector including;

a first buffer having a first input node connected to said first partial signal line for receiving said first output signal and a first output node connected to said digital circuit through said second partial signal line, said first buffer for forming an electrical path between said first input node and said first output node when said first test mode signal takes said active level and bringing said first output node into a high impedance state when said first test mode signal takes said inactive level, and

a first switching circuit connected between said first output node of said first buffer and said first test signal input/output terminal and for being rendered conductive to form an electrical path therebetween when at least one of said first and second test mode signals takes said inactive level and being rendered non-conductive to disconnect said first output node from said first test signal input/output terminal when both of said first and second mode signals take said active level,

said second selector including;

a second buffer having a second input node connected to said third partial signal line for receiving said second output signal and a second output node connected to said analog circuit through said fourth partial signal line, said second buffer for forming an electrical path between said second input node and said second output node when said second test mode signal takes said active level and for bringing said second output node into a high impedance state when said second test mode signal takes said inactive level, and

a second switch circuit connected between said second output node of said second buffer and said second test signal input/output terminal and rendered conductive to form an electrical path therebetween when at least one of said first and second test mode signals takes said inactive level and being rendered non-conductive to disconnect said second output node from said second test signal input/output terminal when both of said first and second test mode signals take said active level.

2. A semiconductor integrated circuit according to claim 1, wherein each of said first and second selectors provides an interface between said analog circuit and said digital circuit such that said analog circuit and said digital circuit are independently testable of one another and such that a condition of an interconnection between said analog circuit and said digital circuit is testable.

3. A semiconductor integrated circuit as claimed in claim 1, wherein said first switch circuit includes:

a third buffer having a third input node connected to said first test signal input/output terminal and a third output node connected to said first output node of said first buffer; and

a fourth buffer having a fourth input node connected to said first output node of said first buffer and a fourth output node connected to said first test signal input/output terminal, and

wherein said second switch circuit includes;

a fifth buffer having a fifth output node connected to said second output node of said second buffer and a fifth input node connected to said second test signal input/output terminal; and

a sixth buffer having a sixth input node connected to said second output node of said second buffer and a sixth output node connected to said second test signal input/output terminal,

each of said third and sixth buffers for forming an electrical path between an associated one of said third and sixth input nodes and an associated one of said third and sixth output nodes when said first test mode signal takes said inactive level and for bringing said associated one of said third and sixth output nodes into a high impedance state when said first test mode signal takes said active level, and

each of said fourth and fifth buffers for forming an electrical path between an associated one of said fourth and fifth input nodes and an associated one of said fourth and fifth output nodes when said second test mode signal takes said inactive level and for bringing said associated one of said fourth and fifth output nodes into a high impedance state when said second test mode signal takes said active level.

4. A semiconductor integrated circuit comprising:

an analog circuit for processing input signals supplied thereto and for producing at least one first output signal;

a digital circuit for processing input signals supplied thereto and for producing at least one second output signal;

a first signal line, coupled between said analog circuit and said digital circuit, for transferring said first output signal to said digital circuit;

a second signal line, coupled between said digital circuit and said analog circuit, for transferring said second output signal to said analog circuit;

a first test mode terminal supplied with a first test mode signal, said first test mode signal taking one of an active level and an inactive level in accordance with operation modes;

a second test mode terminal supplied with a second test mode signal, said second test mode signal taking one of an active level and an inactive level in accordance with operation modes;

a first test signal input/output terminal;

a second test signal input/output terminal;

a first selector, inserted in said first signal line, for dividing said first signal line into first and second partial signal lines and coupled to said first and second test mode terminals and said first test signal input/output terminal, said first selector for forming a signal transmission path between said first and second partial signal lines when said first test mode signal takes said active level, said first selector for disconnecting between said first and second partial signal lines and for forming a signal transmission path between said second partial signal line and said first test signal input/output terminal when said first test mode signal takes said inactive level; and

a second selector, inserted in said second signal line, for dividing said second signal line into third and fourth partial signal lines and coupled to said first and second test mode terminals and said second test signal input/output terminal, said second selector for forming a signal transmission path between said third and fourth partial signal lines when said second test mode signal takes said active level, said second selector for disconnecting between said third and fourth partial signal lines and for forming a signal transmission path between said fourth partial signal line and said second test signal input/output terminal when said second test mode signal takes said inactive level,

said first selector including;

first logic gate means having an input connected to said first partial signal line, for receiving said first output signal and an output connected to said second partial signal line, said first logic gate means being controlled by said first and second mode signals so that when both of said first and second mode signals take said active level, said first logic gate means forms said signal transmission path between said first and second partial signal lines, and when at least one of said first and second test mode signals takes said inactive level, said first logic gate means disconnects between said first and second partial signal lines,

analog switch means having a first end connected to said first partial signal line and a second end connected to said first test signal input/output terminal, said analog switch means being controlled by said second test mode signal to be closed when said second test mode signal takes said inactive level and to be opened when said second test mode signal takes said active level, and

second logic gate means having an input connected to said second end of said analog switch means and an output connected to said second partial signal line, said second logic gate means being controlled by said first test mode signal so that when said first test mode signal takes said inactive level, said second logic gate means forms a signal transmission path between said second end of said analog switch means and said second partial signal line, and when said first test mode signal takes said active level, said second logic gate means disconnects between said second end of said analog switch means and said second partial signal line.

5. A semiconductor integrated circuit as claimed in claim 4, wherein said first logic gate means includes:

a NOR gate having first and second inputs connected to said first and second test mode terminals; and

a first AND gate having a first input connected to said first partial signal line and a second input connected to an output of said NOR gate, and

wherein said second logic gate means includes a second AND gate having a first input connected to said second end of said analog switch means and a second input connected to said first test mode terminal, an output of each of said first and second AND gates being connected to an OR gate having an output connected to said second partial signal line.

6. A semiconductor integrated circuit according to claim 4, wherein each of said first and second selectors provides an interface between said analog circuit and said digital circuit such that said analog circuit and said digital circuit are independently testable of one another and such that a condition of an interconnection between said analog circuit and said digital circuit is testable.

7. A semiconductor integrated circuit comprising:

an analog circuit for processing input signals supplied thereto and for producing at least one first output signal, said analog circuit also having at least one analog signal input;

a digital circuit for processing input signals supplied thereto and for producing at least one second output signal;

a first signal line, coupled between said analog circuit and said digital circuit, for transferring said first output signal to said digital circuit;

a second signal line, coupled between said digital circuit and said analog circuit, for transferring said second output signal to said analog circuit;

a first test mode terminal supplied with a first test mode signal, said first test mode signal taking one of an active level and an inactive level in accordance with operation modes;

a second test mode terminal supplied with a second test mode signal, said second test mode signal taking one of an active level and an inactive level in accordance with operation modes;

a first test signal input/output terminal;

a second test signal input/output terminal;

a first selector, inserted in said first signal line, for dividing said first signal line into first and second partial signal lines and being coupled to said first and second test mode terminals and said first test signal input/output terminal, said first selector for forming a signal transmission path between said first and second partial signal lines when said first test mode signal takes said active level, said first selector for disconnecting between said first and second partial signal lines and for forming a signal transmission path between said second partial signal line and said first test signal input/output terminal when said first test mode signal takes said inactive level;

a second selector, inserted in said second signal line, for dividing said second signal line into third and fourth partial signal lines and being coupled to said first and second test mode terminals and said second test signal input/output terminal, said second selector forming a signal transmission path between said third and fourth partial signal lines when said second test mode signal takes said active level, said second selector for disconnecting between said third and fourth partial signal lines and for forming a signal transmission path between said fourth partial signal line and said second test signal input/output terminal when said second test mode signal takes said inactive level;

a level shifter having an input connected to said analog signal input of said analog circuit, for convening a small-amplitude signal applied to said analog signal input of said analog circuit into a signal having a digital signal amplitude; and

a third selector connected between an output of said level shifter and said digital circuit and being controlled by said first and second test mode terminals so that when said digital circuit is tested, said signal having the digital signal amplitude which is outputted from said level shifter and which is obtained from said small-amplitude signal applied to said analog signal input of said analog circuit, is supplied to said digital circuit.

8. A semiconductor integrated circuit according to claim 7, wherein each of said first and second selectors provides an interface between said analog circuit and said digital circuit such that said analog circuit and said digital circuit are independently testable of one another and such that a condition of an interconnection between said analog circuit and said digital circuit is testable.