Error detection for parallel data transfer between a processor and a peripheral device by comparing regisgers storing a sum of values in bytes of data transferred

• US 5,506,958 A
• Filed: 02/10/1993
• Issued: 04/09/1996
• Est. Priority Date: 02/10/1993
• Status: Expired due to Term

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Conner Peripherals Incorporated (Whitehouse Group Ltd.)
• Inventors: Myran, Mark
• Primary Examiner(s): Nguyen, Hoa T.
• Application Number:
  US08/015,784
• Time in Patent Office: 1,154 Days
• Field of Search: 371/53, 371/37.6, 371/37.7, 371/30, 395/182.16, 395/185.04, 395/185.05, 395/185.07, 395/185.09
• US Class Current: 714/18
• CPC Class Codes: G06F 11/08 Error detection or correction by redundancy in data representation, e.g. by using checking codes
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

A method and apparatus for performing error detection on data transfer through a parallel interface port at a substantially increased data transfer rate with a minimum of handshaking. Blocks of data are transferred between a sending device and a receiving device, and each of the respective devices maintains a checksum. Each checksum comprises an initial value, and added to that value is the value of each data byte transferred through the parallel port interface. After a block of data bytes has been transferred, the checksum maintained by the sending device and the receiving device are compared. If the checksums are equal, no error is assumed to have occurred during the data transfer. If the checksums are not equal, an error is assumed to have occurred during the data transfer, and the data is retransferred with the previously transferred block discarded.

Claims

1. A computer system for transferring of data bytes in a number of data transfer modes and providing error detection during transfer of data bytes over parallel data lines, comprising:

parallel data lines;

a processing unit including;

a parallel interface port connected to the parallel data lines;

a first checkvalue register connected to receive the value of data bytes transferred from the parallel interface port to the parallel data lines, the first checkvalue register being initialized to store a predetermined value prior to transfer of data bytes from the processing unit over the parallel data lines and increased by a value of each data byte transferred from the processing unit after initialization;

comparison means for comparing values stored in the first checkvalue register and a second checkvalue register after a predetermined number of data bytes have been transferred from the processing unit to a memory, the comparison means indicating when a match occurred, or when a match did not occur;

an interface circuit including;

said memory for storing a predetermined number of data bytes, the memory being connected to the parallel data lines;

said second checkvalue register connected to the parallel data lines to receive data bytes transferred to the memory, the second checkvalue register being initialized to store a predetermined value prior to receipt of data bytes by the memory and increased by a value of each data byte received by the memory after initialization;

a control status register storing a data transfer mode indication for controlling of a data transfer mode, the control status register being coupled to the processing unit;

a peripheral device including a peripheral controller connected to the memory; and

wherein the processing unit causes a transfer of the predetermined number of data bytes from the memory to the peripheral controller when the comparison means indicates a match occurred, retransfers the predetermined number of data bytes from the processing unit to the memory when the comparison means indicates a match did not occur, and causes the control status register to change the data transfer mode indication when the comparison means indicates a match did not occur after the predetermined number of data bytes are retransferred a predetermined number of times.

3. The computer system of claim 1 wherein the data transfer mode indication indicates a data transfer rate.

4. A method for determining if an error has occurred during the transfer of data bytes over parallel data lines in a computer system which includes a processor connected to the data lines, the processor including a first checkvalue register, the computer system further including an interface unit including a temporary memory and a second checkvalue register each connected to the parallel data lines, and a peripheral device including a peripheral controller connected to the parallel data lines, the method comprising the steps of:

initializing the first checkvalue register to a predetermined value;

initializing the second checkvalue register to the predetermined value;

transferring data bytes from the processor to the memory;

increasing the first checkvalue register by the value of each data byte transferred from the processor;

increasing the second checkvalue register by the value of each data byte transferred to the memory;

comparing the first and second checkvalue registers after a predetermined number of data bytes have been transferred from the processor to the memory to determine if a match has occurred;

transferring the predetermined number of data bytes from the temporary memory to the peripheral controller if it is determined that a match occurred;

retransferring the predetermined number of data bytes from the processor to the memory if it is determined that a match did not occur; and

changing a mode of data transfer when a match does not occur after the predetermined number of data bytes are retransferred a predetermined number of times.

2. The computer system of claim 6, further comprising a means for overwriting in the memory the predetermined number of data bytes if the comparison means indicates a match did not occur.

5. The method defined by claim 4, further comprising the step of discarding the from the memory the predetermined number of data bytes if a match has not occurred.

6. The computer system of claim 4, wherein the mode of data transfer sets the data transfer rate.