Real-time management system having coprocessors allocated time slices of different durations to functions and processors executed functions simultaneously in accordance with the time allocation

• US 5,506,963 A
• Filed: 10/02/1992
• Issued: 04/09/1996
• Est. Priority Date: 10/03/1991
• Status: Expired due to Fees

• Current Assignee: Sextant Avionique
• Original Assignee: Sextant Avionique
• Inventors: Ducateau, Michel, Sers, Jean-Marie, Pain, Isabelle
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Luu, Le Hien
• Application Number:
  US07/955,446
• Time in Patent Office: 1,285 Days
• Field of Search: 395/550, 395/650, 395/325, 364/131, 364/200, 364/900, 177/25.15
• US Class Current: 718/107
• CPC Class Codes: G06F 9/4887 involving deadlines, e.g. rate based, periodic

Abstract

The method embodying the invention comprises management by a coprocessor of the time slicing, from a pre-established frame, of the processing cycle of the processor, into slices of possibly different durations, of the allocation of the time slices to the different functions installed according to one or plural pre-established layouts, of the saving at the end of the machine context slice of the function being processed, this with a view to resuming this function during the following slice associated with it and of the loading, at the start of a new slice, of the machine context linked with the activating of the function associated with this slice and which was previously saved at the end of a previous slice corresponding to this function. The invention applies to the optimizing and security of real-time management in modular avionics architectures.

Claims

1. A device for managing a real-time context of a system which comprises at least one processor working with a processor cycle so as to execute in apparent simultaneity several functions, each comprising an assembly of tasks providing high level services, and a coprocessor in the form of a component connected to said processor and availing of data relating to said real-time context, said coprocessor comprising means for managing the following steps:

i) time slicing, from a pre-established frame, of said processing cycle into time slices of possible different durations;

ii) allocating to each of said functions a corresponding set of time slices, according to a predetermined layout, the assembly of tasks of said function being activatable exclusively during the time slices of the allocated set, and being put in a frozen state outside the time slices of said allocated set;

iii) saving, at the end of each of said time slices a machine context of the function to be processed before effecting a slice change;

iv) when a new time slice allocated to one determined function is starting, loading the machine context previously saved at the end of a previous time slice allocated to this determined function, electing a top priority task to be executed belonging to said determined function, and activating said determined function so as to execute at first said priority task with the loaded machine context, wherein said coprocessor comprises at least three automata;

first automaton for managing exchanges between said coprocessor and said processor, via a local memory, a swap memory, a common bus, a local exchange bus BiE and a hardware event bus;

a second automaton for managing said functions during said time slices;

a third automaton for managing certain real-time objects linked with an active function being performed during the time slice in process, especially for managing queues of eligible tasks awaiting said processor, for managing local time such as timeouts, for managing queues awaiting mailboxes and semaphores, for managing tasks awaiting global or local events and for handling external interruptions;

these three automata communicating with one another by means of a bus inside the coprocessor component, primitives relating to global events being broadcast on said hardware event bus.

2. The device as claimed in claim 1, which comprises mechanisms ensuring segregation of real-time objects specific to the functions managed in said processor with which said coprocessor component is associated.

3. The device as claimed in claim 1, which comprises mechanisms ensuring switching from an aborted function to a newly processed function corresponding to an end of the time slice allocated to said aborted function and to a new time slice allocated to said newly processed function.

4. The device as claimed in claim 1 which also comprises copy automata for transferring data independently of said processor, between a source memory and a destination memory.

5. The device as claimed in claim 1, which comprises the following seven automata:

a processor communications automaton used to manage exchanges with said processor, including a distribution of processings over the other automata as a function of primitives requested by said processor;

a time management automaton for managing said absolute time, said time slices and local time-related objects linked with said functions, said time management automaton segregating local objects of each function within the coprocessor component;

a semaphore automaton for managing binary semaphores and the counter semaphores and associated queues of tasks on stand-by;

a mailbox automaton for managing mailboxes and associated queues of tasks on stand-by;

a scheduler automaton for managing queues of eligible tasks on stand-by and therefore capable of transmitting an interruption to said processor;

an event automaton for managing events including tasks awaiting an event, and handling the external interruptions;

a copy automaton for managing copying of memory blocks.

6. A method for managing a real-time context of a system which comprises at least one processor with a processor cycle so as to execute independently and in apparent simultaneity several functions, each of said functions comprising an assembly of tasks providing high level services, and a coprocessor in the form of a component connected to said processor and availing of data relating to said real-time context, said method comprising management by said coprocessor of the following steps:

i) time slicing, from a pre-established frame of said processing cycle into time slices of possibly different durations,

ii) allocating to each of said functions a corresponding set of time slices, according to a predetermined layout, the assembly of tasks of said function being activatable and processed exclusively during the time slices of the allocated set, and being put in a frozen state outside the time slices of said allocated set;

iii) saving, at the end of each of said time slices, a machine context of the processed function before effecting a slice change;

iv) when a new time slice allocated to one determined function is starting, loading the machine context previously saved at the end of a previous time slice allocated to this determined function, and processing said determined function within said new time slice by scheduling and executing the tasks of said determined function in relation to respective priorities of said tasks and of said real-time context.

7. The method as claimed in claim 6, wherein said processor comprises two levels of execution:

a first level called "Application Supervisor" on which a function will rely to schedule tasks in relation to the real-time context and to resources and events required by the function to perform within said processor;

a second level called "Sequency Supervisor" which provides services needed for time-sharing of said processor between the different functions installed in said processor and management of global events.

8. The method as claimed in claim 6, wherein said coprocessor component comprises a scheduler for managing functions by time slices by means of a Sequencing Supervisor, and for performing services in the form of primitives by said processor to enable real-time linking of the functions, within corresponding time slices.

9. The method as claimed in claim 8, wherein said coprocessor functions in two operating modes:

a slave type operating mode, in which said coprocessor is perceived by the processor as memory;

this mode being used to execute primitives and being translated by reading and writing at a coprocessor address;

a master type operating mode, in which it can read or write data in a local memory.

10. The method as claimed in claim 6, wherein at the end of a time slice, said coprocessor generates an interruption destined for indicating to the processor that it must abort the function in process to take up the function indicated by said coprocessor, and wherein until receipt of said interruption, said processor performs the following successive stages:

execution of a sequence enabling it to save a minimum machine context of said function in process for proper resumption at a next associated time slice;

transmission of a message to said coprocessor for advising it that it is ready to receive a number of a newly active function as well as a top priority task to be executed belonging to said function;

reloading of the machine context linked with an activation of said function and with an election of said task of which the context may have been saved at the end of a last time slice relating to a newly reactivated task.

11. The method as claimed in claim 10, which uses several modules, each comprising a processor connected to a coprocessor, said method further comprising a periodical synchronization phase for maintaining a system time common to all the coprocessors for enabling synchronization of slice changes in the different modules.

12. The method as claimed in claim 6, which uses a time reference generated by a backpanel bus interface component and wherein said slice change is commanded by said component which alerts said processor by means of an interruption, said processor then executing a primitive which orders said coprocessor to change applications, and said coprocessor subsequently checking that said slice change is indeed within a time window.