System with multiple interface logic circuits including arbitration logic for individually linking multiple processing systems to at least one remote sub-system
First Claim
1. A data processing and transmission network having a fault tolerant coupling of a plurality of information processing system, the network including:
- a plurality of information processing systems, each information processing system including a system processsing device that includes a processor interface logic circuits;
a plurality of shared sub-systems remote form the information processing systems, each shared sub-system including an I/O bus and an associated group of I/O bus interface logic circuits;
multiple data transmission links for serial and bidirectional transmission of data between the system processing devices and the shared sub-systems and comprised of a plurality of link sets, the links of each link set being coupled to an associated one of the system processing devices and further being individually connected to different ones of the shared sub-systems via the associated group I/O interface logic circuits, with each of the I/O bus interface logic circuits being coupled between its associated I/O bus and one of the data transmisssion links, whereby each link set operatively couples its associated system processing device with all of the shared sub-systems;
wherein each of the data transmission links of the associated link set is connected at one end to the processor interface logic circuit of the associated system processing device and at the opposite end to one of the I/O bus interface logic circuits; and
wherein each of the sub-systems further includes an arbitration means including arbitration logic circuits in the I/O bus interface logic circuits, for determined priority among the I/O bus interface logic circuits of the group contending for control of the associated I/O bus, for resolving contentions among the processing devices for control of the associated I/O bus.
1 Assignment
0 Petitions
Accused Products
Abstract
A data processing and transmission network includes plural information processing systems and shared sub-systems remote from the information processing systems. Each shared sub-system includes an I/O bus and a plurality of I/O bus interface logic circuits coupled to the bus. Each interface logic circuit is coupled to one of the system processing devices via a bidirectional fiber optic link, and thereby couples its associated processing device to the I/O bus. Further fiber optic links couple each system processing device to the I/O bus of each remaining sub-system through an associated I/O bus interface logic circuit. Each sub-system further includes multiple I/O devices, each device coupled to a device controller which in turn is coupled to the I/O bus. The bus interface logic circuits and device controllers incorporate arbitration circuitry and communicate with one another via their associated I/O bus, thus to resolve contentions for control of the bus at the sub-system level rather than at the system processor level. These features provide a network with a high degree of redundancy, substantially reduced data access times, and flexibility in network configurations. Regardless of network size, each sub-system I/O device is equally available to all system processing devices, and each system processing device is transparent to the other system processors.
-
Citations
32 Claims
-
1. A data processing and transmission network having a fault tolerant coupling of a plurality of information processing system, the network including:
-
a plurality of information processing systems, each information processing system including a system processsing device that includes a processor interface logic circuits; a plurality of shared sub-systems remote form the information processing systems, each shared sub-system including an I/O bus and an associated group of I/O bus interface logic circuits; multiple data transmission links for serial and bidirectional transmission of data between the system processing devices and the shared sub-systems and comprised of a plurality of link sets, the links of each link set being coupled to an associated one of the system processing devices and further being individually connected to different ones of the shared sub-systems via the associated group I/O interface logic circuits, with each of the I/O bus interface logic circuits being coupled between its associated I/O bus and one of the data transmisssion links, whereby each link set operatively couples its associated system processing device with all of the shared sub-systems; wherein each of the data transmission links of the associated link set is connected at one end to the processor interface logic circuit of the associated system processing device and at the opposite end to one of the I/O bus interface logic circuits; and wherein each of the sub-systems further includes an arbitration means including arbitration logic circuits in the I/O bus interface logic circuits, for determined priority among the I/O bus interface logic circuits of the group contending for control of the associated I/O bus, for resolving contentions among the processing devices for control of the associated I/O bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
-
-
16. In a data processing network including a plurality of information processing systems, each system including a system processing device having a processor interface logic circuit;
- a plurality of sub-systems remote from the information processing systems, each sub-system including and I/O bus and an associated group of I/O bus interface logic circuits; and
multiple fiber optic links between the system processing devices and the buses for transmission of data between each of the system processing devices and all of the sub-systems a process for transmission the data throughout the network, including the step of;converting the data from electronic form to optical form for transmission over one of the fiber optic links; converting the data from optical form to electronic form for reception of the data into the processor interface logic circuit of one of the system processing devices, or into one of the I/O bus interface logic circuits; utilizing arbitration control circuitry within the I/O bus interface logic circuits of the group associated with each of the sub-systems for resolving contentions among the system processing devices for control of the associated I/O bus; and transmitting data from a first one of the system processing devices to a second one of the system processing devices via the associated one of the I/O busses in response to one of the first and second system processing devices gaining control of the I/O bus.
- a plurality of sub-systems remote from the information processing systems, each sub-system including and I/O bus and an associated group of I/O bus interface logic circuits; and
-
17. A data processing and transmission network having a fault tolerant coupling of a plurality of remote information processing systems, said network including:
-
a plurality of remote information processing systems, each system including a system processing device, with each of the system processing devices including a processor interface logic circuit; a plurality of shared I/O busses remote from the information processing systems; multiple I/O bus interface logic circuits comprised of a plurality of groups of the I/O bus interface logic circuits, the individual I/O bus interface logic circuits of each said group being operatively coupled with an associated one of the shared I/O busses; multiple data transmission links comprised of a plurality of link sets, the individual data transmission links of each set being coupled to the processor interface logic circuit of an associated one of the system processing devices, with each data transmission link of the set further being uniquely coupled to a different one of the shared I/O busses through a selected one of the I/O bus interface logic circuits, whereby all of the system processing devices are coupled to each one of the I/O busses through the associated group of I/O bus interface logic circuits; and an arbitration means associated with each of the I/O busses, comprising arbitration logic in each of the I/O bus interface logic circuits, for resolving contentions among the system processing devices for control of that I/O bus. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
-
-
25. A data processing and transmission network for coupling a plurality of remote information processing systems, said network including:
-
a plurality of remote information processing systems, each system including a system processing device; a shared I/O bus remote from the information processing systems; a set of device controllers coupled to the I/O bus with each device controller including an arbitration logic circuit and a plurality of data storage devices coupled to the device controllers; a plurality of I/O bus interface logic circuits operatively coupled with the I/O bus; and a plurality of data transmission links for serial and bidirectional transmission of data, each of the data transmission links being coupled to one of the system processing devices and to an associated one of the I/O bus interface logic circuits, thereby to couple its associated system processing device with the shared I/O bus; wherein each of the I/O bus interface logic circuits includes an arbitration logic circuit, said arbitration logic circuits communicating with one another via the shared I/O bus to resolve contentions among the system processing devices for control of the I/O bus; and wherein the arbitration logic circuits of the bus interface logic circuits and the arbitration logic circuits of the controllers cooperate to resolve contentions for control of the I/O bus among the system processing devices and the I/O devices. - View Dependent Claims (26)
-
-
27. In a network including a plurality of information processing systems each having a system processing device with a processor interface logic circuit, and at least one sub-system remote from the information processing systems and comprising an I/O bus, a plurality of data receiving means coupled to the I/O bus wherein each of the data receiving means is capable of receiving data from one of the information processing systems and placing said data on the I/O bus and wherein each data receiving means includes an arbitration logic circuit, and a plurality of data transmission means coupled to the I/O bus wherein each of the data transmission means is capable of reading data on the I/O bus and transmitting the data to one of the information processing systems;
- a process for transmitting data among the information processing systems, comprising the steps of;
transmitting data from a first one of the information processing systems via the processor interface logic circuit of an associated first system processing device to a first one of the data receiving means in the remote sub-system; receiving the data with the first data receiving means; using the arbitration logic circuits of said plurality of data receiving means to resolve a contention for control of the I/O bus in favor of said first data receiving means, and using the first data receiving means to place the data on the I/O bus in the remote sub-system; reading the data from the I/O bus in the remote sub-system with a selected first one of the data transmission means in the remote sub-system; and transmitting the data from the selected first data transmission means to a second information processing system of the network. - View Dependent Claims (28)
- a process for transmitting data among the information processing systems, comprising the steps of;
-
29. An apparatus for transmitting data among a plurality of remote information processing systems, including:
-
a data transmission sub-system set comprised of at least one sub-system shared by a plurality of information processing systems, with the information processing systems being remote from one another and from the at least one sub-system, wherein each of the information processing systems includes a system processing device having a processor interface logic circuit; wherein the sub-system includes an I/O bus, and a group of associated I/O bus interface logic circuits operatively coupled to the I/O bus, each I/O bus interface logic circuit of the group including an arbitration logic circuit; wherein each of the I/O bus interface logic circuits of the group further is adapted for operable coupling to the system processing device of a uniquely associated one of the information processing systems via the processor interface logic circuit of the system processing device, to enable data transmission between each of the information processing systems and the I/O bus via the associated I/O bus interface logic circuit; and wherein the arbitration logic circuits communicate with one another via the I/O bus to resolve contentions among the information processing systems for control of the I/O bus. - View Dependent Claims (30, 31)
-
-
32. A data processing and transmission network having a fault tolerant coupling of a plurality of remote information processing systems, said network including:
-
a plurality of remote information processing systems, each system including a system processing device; a plurality of shared I/O busses remote from the information processing systems; multiple I/O bus interface logic circuits comprised of a plurality of groups of the I/O bus interface logic circuits, the individual I/O bus interface logic circuits of each said group being operatively coupled with an associated one of the shared I/O busses; multiple data transmission links comprised of a plurality of links sets, the individual data transmission links of each set being coupled to an associated one of the system processing devices, with each data transmission link of the set further being uniquely coupled to a different one of the shared I/O busses through a selected one of the I/O bus interface logic circuits, whereby all of the system processing devices are coupled to each one of the I/O busses through the associated group of I/O bus interface logic circuits; an arbitration means associated with each of the I/O busses comprising arbitration logic in each of the I/O bus interface logic circuits, for resolving contentions among the system processing devices for control of that I/O bus; and multiple device controllers comprised of a plurality of device controller sets, the device controllers of each controller set being coupled to an associated one of the I/O busses, and a plurality of I/O devices coupled to the device controllers, wherein said arbitration means comprises arbitration logic in the I/O bus interface logic circuits and in the device controllers.
-
Specification