Printer port adapter with overlaid one-wire interface for electronic key

• US 5,506,991 A
• Filed: 12/19/1990
• Issued: 04/09/1996
• Est. Priority Date: 05/15/1989
• Status: Expired due to Term

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Dallas Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Lehmann, Guenter H., Curry, Stephen M., Deierling, Kevin E., Bolan, Michael L., Payne, William L. II
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): MOHAMED, AYNI Y
• Application Number:
  US07/631,929
• Time in Patent Office: 1,938 Days
• Field of Search: 395/101, 395/800, 395/325
• US Class Current: 710/62
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 3/0383 Signal control means within the pointing device
• CPC Class Codes: G06F 3/04897 Special input arrangements or commands for improving display capability
• CPC Class Codes: G06K 19/047 the record carrier being shaped as a coin or a gambling token
• CPC Class Codes: G06K 19/0706 the battery being replaceable
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 19/07735 the record carrier comprising means for protecting against electrostatic discharge
• CPC Class Codes: G06K 19/07743 External electrical contacts
• CPC Class Codes: G06K 7/0021 for reading/sensing record carriers having surface contacts
• CPC Class Codes: G06K 7/0086 the connector comprising a circuit for steering the operations of the card connector
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: G11C 8/20 Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access
• CPC Class Codes: H01L 23/58 Structural electrical arrangements for semiconductor devices not otherwise provided for , e.g. in combination with batteries H01L23/49593, H01L23/49596 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H04B 1/403 using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency
• CPC Class Codes: H05K 1/0393 : Flexible materials H05K1/038 takes precedence; specific organic compositions are classified in H05K1/0313 and subgroups
• CPC Class Codes: H05K 3/325 : by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor adaptations of leads inserted in holes for press-fit connections H05K3/308

Abstract

A printer port adapter which permits electronic keys to be accessed through the printer port of the PC, without disrupting the normal operation of the printer port in any mode of operation whatsoever. The electronic keys used have a one-wire signal interface, and this interface can be inserted into the full standard ISA printer port pin assignment, as well as the all known nonstandard additional assignments which have been overlaid onto the standard printer port.

Claims

1. An electronic system, comprising:

(a) a plurality of complementary multipin connectors, each complementary multipin connector of said plurality of complementary multipin connectors having at least one pin and at least one internal electrical connection each complementary multipin connector of said plurality of complementary multipin connectors interconnected via said at least one internal electrical connection of each complementary multipin connector of said plurality of complementary multipin connectors, a first complementary multipin connector of said plurality of complementary multipin connectors electrically coupled to a first electrical device via said at least one pin of said fist complementary multipin connector and a second complementary multipin connector of said plurality of complementary multipin connectors electrically coupled to a second electrical device via said at least one pin of said second complementary multipin connector;

(b) an electronic key having a firs terminal selectively electrically coupled to said at least one internal electrical connection of said first complementary multipin connector of said plurality of complementary multipin connectors and a second terminal selectively electrically coupled to said at least one internal electrical connection of said second complimentary multipin connector of said plurality of complementary multipin connectors, said first terminal electrically coupled to at least one internal electrical connection that is internally electrically coupled to provide a one-wire signal interface to said electronic key, said first terminal internally electrically coupled to said second terminal within said electronic key, said electronic key selectively regulates flow of information between said first and second terminals; and

(c) said first terminal has a voltage level, said one-wire signal interface is implemented by holding said first terminal to a first voltage level for a first time period, creating a transition between said first voltage level and a second voltage level, holding said first terminal to said second voltage level for a second time period, and selectively sampling said voltage level of said first terminal to determine whether said data value is a first data value or a second data value at a first time, said data value transferred via said one-wire signal interface comprises at least one self-synchronized bit, each self-synchronized bit of said at least one self-synchronized bit is independent of every other self-synchronized bit of said at least one self-synchronized bit.

2. The device of claim 1, wherein each complementary multipin connector of said plurality of complementary multipin connectors are physically and electrically compatible with a standard connector and port definitions.

3. The device of claim 1, further comprising a resistor and a diode electrically coupled in parallel between said first terminal of said electronic key and one internal connection of said at least one internal electrical connection of said first complementary multipin connectors of said plurality of complementary multipin connectors.

4. The device of claim 2, wherein said standard connector and port definitions are a personal computer printer ports.

5. The device of claim 1, wherein said plurality of complementary multipin connectors are housed in a common housing.

6. The device of claim 1, wherein said second complementary multipin connector is a male connector and said first complementary multipin connector is a female connector that are mutually complementary.

7. The device of claim 1, wherein said first electrical device is a printer and said second electrical device is a personal computer.

8. The device of claim 1, wherein said first electrical device and said second electrical device conduct operations independently and in conjunction with each other and said electronic key does not disturb said operations.

9. The device of claims 7, wherein said printer and said personal computer conduct a plurality of operations independently and in conjunction with each other and said electronic key does not interfere with said plurality of operations.

10. The device of claim 1, wherein a second electronic key having a first terminal and a second terminal, said first terminal of said second electronic key electrically coupled to said at least one internal electrical connection of said first complementary multipin connector of said plurality of complementary multipin connectors and said second complementary multipin connector of said plurality of complementary multipin connectors and said second terminal of said second electronic key electrically coupled to said at least one internal electrical connection of said first complementary multipin connector of said plurality of complementary multipin connector, said first terminal and said second terminal of said second electronic key internally electrically coupled together within said second electronic key to provide said one-wire signal interface to said at least one internal electrical connection of said first complementary multipin connector and to said second complementary multipin connector of said plurality of complementary multipin connectors.

11. The device of claim 10, wherein said one-wire signal interface also exists between said electronic key and said second electronic key.

12. The device of claim 1, further comprising a timing control system electrically coupled to each complementary multipin connector of said plurality of complementary multipin connectors to control timing operations selected from the group consisting of determining how long to hold said first terminal to said first voltage level for said first time period, determining when to create said transition between said first voltage level and said second voltage level, determining how long to hold said first terminal to said second voltage level for said second time period, and determining when to sample said voltage level of said first terminal to determine whether said data value is said first data value or said second data value at said first time period, so that said one-wire signal interface transfers said at least one self-synchronized bit, each self-synchronized bit of said at least one self-synchronized bit is independent of each other.

13. The device of claim 12, wherein said timing control system comprises a microprocessor to control and manage said timing operations.

14. The device of claim 13, wherein said first electrical device is a personal computer and said second electrical device is a printer, said microprocessor is inside said personal computer and used by said personal computer to coordinate other activities.

15. The device of claim 1, said first terminal internally electrically coupled to said second terminal within said electronic key to provide a three-wire signal interface.

16. The device of claim 1, wherein said complementary multipin connectors of said plurality of complementary multipin connectors is electrically coupled to said first electrical device via a coaxial cable, said coaxial cable when combined with said at least one pin and said at least one internal electrical connection of each complementary multipin connector of said plurality of complementary multipin connectors electrically couple said first electrical device and to said second electrical device.

17. The device of claim 1, wherein said first electrical device is a coaxial cable and said second electrical device is a host computer.

18. The device of claim 17, wherein said coaxial cable connects to said second electrical device.

19. The device of claim 1, wherein a test password from said second electrical device is sent to said electronic key via said first terminal and said one-wire signal interface and said electronic key compares said test password to a password stored in an internal memory in said electronic key to determine if said test password and said password match up, and, if said test password and said password match up, then said electronic key transmits secret data from said internal memory in said electronic key.

20. The device of claim 19, further wherein if said test password and said password do not match up, then said electronic key transmits random information generated by a random number generator.

21. The device of claim 1, wherein said host device initiates a search to poll said electronic key that entails resetting said electronic-key and issuing a search data command on said one-wire bus.

22. The device of claim 19, wherein said password comprises 8 bytes of information.

23. The device of claim 7, wherein said personal computer has at least one input and at least one output and said electronic key regulates a flow of information between said at least one input and said at least one output of said personal computer and said first and second terminals of said electronic key.

24. An authorization system, comprising:

a first connector having at least one pin and at least one internal connection;

a second connector having at least one pin and at least one internal connection, said first connector and said second connector electrically coupled together via said at least one internal connection of said first connector and said at least one internal connection of said second cormcorox;

an electronic key having a first terminal and a second terminal, said first terminal of said electronic key selectively electrically coupled to said at least one internal connection of said first connector and said second terminal of said electronic key selectively electrically coupled to at least one internal connection of said second connector; and

control circuitry electrically coupled between said first terminal of said electronic key and said second terminal of said electronic key via a one-wire signal interface established between said first terminal of said electron key and said second terminal of said electronic key, said first terminal of said electronic key has a voltage level, said one-wire signal interface is implemented by holding said first terminal of said electronic key to a first voltage level for a first time period, creating a transition between said first voltage level and a second voltage level, holding said first terminal of said electronic key to said second voltage level for a second time period, and selectively sampling said voltage level of said first terminal of said electronic key to determine whether said data value is a first data value or a second data value at a first time, said data value transferred via said one-wire signal interface comprises at least one self-synchronized bit, each self-synchronized bit of said at least one self-synchronized bit is independent of every other self-synchronized bit of said at least one self-synchronized bit.

25. The authorization system of claim 24, wherein said first connector and said second connector are physically and electrically compatible with a standard connector and port definitions.

26. The authorization system of claim 24, wherein said control circuitry comprises a resistor and a diode electrically coupled in parallel between said first terminal of said electronic key and one internal connection of said at least one internal connection of a connector selected from the group consisting of said first connector or said second connector.

27. The authorization system of claim 25, wherein said standard connector and said port definitions are a personal computer printer ports.

28. The authorization system of claim 24, wherein said first connector and said second connector are housed in a common housing.

29. The authorization system of claim 24 wherein said first connector and said second connector are mutually complementary.

30. The authorization system of claim 24, wherein said first connector is electrically coupled to a first electrical device and said second connector is electrically coupled to a second electrical device.

31. The authorization system of claim 30, wherein said first electrical device is a printer and said second electrical device is a personal computer.

32. The authorization system of claim 30, wherein said first electrical device and said second electrical device transfer information therebetween and said electronic key does not disturb said transfer of information.

33. The authorization system of claim 31, wherein said printer and said personal computer transfer information therebetween and said electronic key does not interfere with said transfer of information.

34. The authorization system of claim 24, further comprising

a second electronic key having said first terminal and a second terminal, said first terminal of said second electronic key selectively electrically coupled to said at least one internal connection of one of said first connector an a second terminal of said second electronic key selectively electrically coupled to said at least one internal connection of said second connector and

second control circuitry electrically coupled between said first terminal of said second electronic key and said second terminal of said second electronic key to regulate a flow of information between said first terminal of said second electronic key and said second terminal of said second electronic key, said second electronic key selectively regulates flow of information between via a one-wire signal interface established between said first terminal of said second electronic key and second terminals of said second electronic key, said first terminal of said second electronic key has a third voltage level, said one-wire signal interface is implemented by holding said first terminal of said second electronic key to said first voltage level for said first time period, creating said transition between said first voltage level and said second voltage level, holding said first terminal to said second voltage level for said second time period, and selectively sampling said bird voltage level of said first terminal of said second electronic key to determine whether said data value is said first data value or said second data value at said first time, said data value transferred via said one-wire signal interface comprises said at least one self-synchronized bit, said each self-synchronize bit of said at least one self-synchronized bit is independent of every other self-synchronized bit of said at least one self-synchronized bit.

35. The authorization system of claim 24, wherein said one-wire signal interface exists between said electronic key and said second electronic key.

36. The authorization system of claim 24, wherein said one-wire signal interface communicates at least one communication signal, said at least one communication signal having timing requirements, said timing requirements controlled by a timing control system.

37. The authorization system of claim 36, wherein said timing control system comprises a microprocessor to control and manage said timing requirements.

38. The device of claim 37, wherein said first connector is electrically coupled to a personal computer and said second connector is connected to a printer, said microprocessor residing inside said personal computer and used by said personal computer to coordinate other activities.

39. The device of claim 24, wherein said first connector and said second connector connect to a coaxial cable, said coaxial cable when combined with said at least one pin and said at least one internal electrical connection of said first connector and said at least one pin and said at least one internal electrical connection of said second connector electrically couple said first electrical device and to said second electrical device.

40. The device of claim 38, wherein a test password is sent to said first electrical device and said first electrical device compares said test password to a password stored in an internal memory in said electrical key to determine if said test password and said password match up, and, if said test password and said password match up, then said electrical key transmits secret data from said internal memory in said electrical key.

41. The device of claim 40, further wherein if said test password and said password do not match up, then said electrical key transmits random information generated by a random number generator.

42. An authorization system, comprising:

a first connector having at least one pin and at least one internal electrical connection;

a second connector having said at least one pin and said at least one internal electrical connection, said first connector and said second connector electrically coupled via said at least one internal electrical connection of said first connector and said second connector, said first connector and said second connector housed in a common housing, said at least one pin of said first connector exposed externally from said common housing, said at least one pin of said second connector exposed externally from said common housing; and

an electronic key having a first terminal selectively electrically coupled to a first internal electrical connection of said at least one internal electrical connection of said first connector and a second internal electrical connection of said at least one internal electrical connection of said first connector and a second terminal selectively electrically coupled to a third internal connection of said at least one internal electrical connection of said at least one internal electrical connection of said second connector; and

control circuitry electrically coupled between said first internal electrical connection of said first connector and said second internal electrical connection of said first connector to regulate a flow of information between;

said first internal electrical connection and said second internal electrical connection of said first connector via a one-wire signal interface established between said first terminal of said second electronic key and second terminals of said second electronic key, said first terminal of said second electronic key has a voltage level, said one-wire signal interface is implemented by holding said first terminal of said second electronic key to said first voltage level for said first time period, creating said transition between said first voltage level and said second voltage level, holding said first terminal to said second voltage level for said second time period, and selectively sampling said voltage level of said first terminal of said second electronic key to determine whether said data value is said first data value or said second data value at said first time, said data value a transferred via said one-wire signal interface comprises said at least one self-synchronized bit, said each self-synchronize bit of said at least one self-synchronized bit is independent of every other self-synchronized bit of said at least one self-synchronized bit.

43. The authorization system of claim 42, wherein said first connector is connected to a first electrical device and said second connector is connected to a second electrical device.

44. The authorization system of claim 43, wherein said first electrical device is a personal computer and said second electrical device is a printer and said at least one pin of said first connector plugs into a parallel port of said personal computer.

45. The authorization system of claim 42, wherein said first electrical device and said second electrical device conduct operations to transfer information between each other and said electronic key does not disturb said operations.