SOI DRAM with field-shield isolation and body contact

• US 5,508,219 A
• Filed: 06/05/1995
• Issued: 04/16/1996
• Est. Priority Date: 06/05/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bronner, Gary B., DeBrosse, John K., Mandelman, Jack A.
• Primary Examiner(s): Thomas, Tom
• Application Number:
  US08/461,958
• Time in Patent Office: 316 Days
• Field of Search: 437/21, 437/47, 437/52, 437/60, 437/919, 257/300, 257/301, 257/305
• US Class Current: 438/152
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate

Abstract

An SOI deep-trench DRAM having body contacts and field shield isolation makes contact between the SOI device layer and the field shield layer at selected sites between adjacent deep trench capacitors. The field shield layer is biased negative to provide better isolation and to set the body potential of the array transistors.

Claims

1. A method of forming an SOI DRAM having a memory array having transistor body contacts in the memory array comprising the steps of:

preparing an SOI wafer having a semiconducting substrate, a semiconductor device layer above said substrate and an insulating layer between said substrate and said device layer;

forming a set of capacitors in contact with said semiconducting substrate in said memory array;

forming an isolation dielectric layer over said set of capacitors in said memory array;

forming a set of body contact apertures extending down through said isolation dielectric layer to said device layer;

forming a field shield having a field shield top surface and in electrical contact with said device layer in said memory array though said set of body contact apertures, thereby forming a set of body contacts in said body contact apertures;

forming a set of parallel active area apertures, each having an active area axis, in said field shield, at least some of said set of parallel active area apertures being adjacent to a member of said set of body contacts; and

forming a set of transistors, having transistor bodies, in said device layer and below said active area apertures.

2. A method of forming an SOI DRAM according to claim 1, in which:

said step of forming a set of capacitors in said memory array comprises a step of forming a set of deep trenches through said device layer and said insulating layer and extending into said substrate; and

forming a set of capacitors in said set of deep trenches.

3. A method of forming an SOI DRAM according to claim 2, in which:

said step of forming a set of transistors includes a step of forming a set of conductive gate contacts within said set of active area apertures and having a gate contact top surface coplanar with said field shield top surface.

4. A method of forming an SOI DRAM according to claim 3, further including a step of forming word lines connecting a plurality of said gate contacts along an axis perpendicular to said active area axes, said word lines being deposited on said gate contact top surface and said field shield top surface.

5. A method of forming an SOI DRAM according to claim 1, in which said steps of forming capacitors and transistors include forming within said active area apertures at least two DRAM cells along said active area axis, each cell containing a capacitor and a transistor connected to said capacitor, at least one of said capacitors being adjacent to a body contact area in said device layer.

6. A method according to claim 5, in which said at least two DRAM cells comprise first and second DRAM cells, said capacitors of said first and second cells being at opposite ends of said active area apertures, said first and second cells being separated by a common contact.

7. A method of forming an SOI DRAM according to claim 2, in which said steps of forming capacitors and transistors include forming within said active area apertures at least two DRAM cells along said active area axis, each cell containing a capacitor and a transistor connected to said capacitor, at least one of said capacitors being adjacent to a body contact area in said device layer.

8. A method according to claim 7, in which said at least two DRAM cells comprise first and second DRAM cells, said capacitors of said first and second cells being at opposite ends of said active area apertures, said first and second cells being separated by a common contact.

9. A method of forming an SOI DRAM having a memory array containing a first polarity of transistors and CMOS support circuitry containing said first polarity of transistors and a second polarity of transistors opposite said first polarity, those of said first polarity of transistors within said array having body contacts, comprising the steps of:

preparing an SOI wafer having a semiconducting substrate, a semiconductor device layer above said substrate and an insulating layer between said substrate and said device layer;

forming a set of capacitors in contact with said semiconducting substrate in said memory array;

forming an isolation dielectric layer over said set of capacitors in said memory array;

forming a set of body contact apertures extending down through said isolation dielectric layer to said device layer;

forming a field shield having a field shield top surface and in electrical contact with said device layer in said memory array though said set of body contact apertures, thereby forming a set of body contacts in said body contact apertures;

forming a set of parallel active area apertures, each having an active area axis, in said field shield, at least some of said set of parallel active area apertures being adjacent to a member of said set of body contacts; and

simultaneously forming a first set of transistors of said first polarity in said device layer and below said active area apertures and a second set of transistors of said first polarity in said device layer in said support circuitry.

10. A method of forming an SOI DRAM according to claim 9, in which:

said step of forming a set of capacitors in said memory array comprises a step of forming a set of deep trenches through said device layer and said insulating layer and extending into said substrate; and

forming a set of capacitors in said set of deep trenches.

11. A method of forming an SOI DRAM according to claim 10, in which:

said step of forming a set of transistors includes a step of depositing a first gate conductive layer inside and outside said array, forming a set of conductive gate contacts from said first gate conductive layer within said set of active area apertures and having a gate contact top surface substantially coplanar with said field shield top surface and with a first gate contact conductive layer top surface outside said array.

12. A method of forming an SOI DRAM according to claim 11, further including steps of depositing a second gate conductive layer in and outside said array, thereby forming a composite gate conductive layer outside said array;

patterning said second gate conductive layer to form word lines connecting a plurality of said gate contacts along an axis perpendicular to said active area axes in said array, said word lines being deposited on said gate contact top surface and said field shield top surface in said array, and patterning composite gate conductive layer to form transistor gates outside said array.

13. A method of forming an SOI DRAM according to claim 9, in which said steps of forming capacitors and transistors include forming within said active area apertures at least two DRAM cells along said active area axis, each cell containing a capacitor and a transistor connected to said capacitor, said capacitors being separated along said active area axis by a body contact area in said device layer.

14. A method according to claim 13, in which said at least two DRAM cells comprise first, second, third and fourth DRAM cells, said capacitors of said second and third cells being separated along said active area axis by said body contact area in said device layer.

15. A method of forming an SOI DRAM according to claim 10, in which said steps of forming capacitors and transistors include forming within said active area apertures at least two DRAM cells along said active area axis, each cell containing a capacitor and a transistor connected to said capacitor, said capacitors being separated along said active area axis by a body contact area in said device layer.

16. A method according to claim 15, in which said at least two DRAM cells comprise first, second, third and fourth DRAM cells, said capacitors of said second and third cells being separated along said active area axis by said body contact area in said device layer.