Trench gate type insulated gate bipolar transistor

• US 5,508,534 A
• Filed: 02/07/1995
• Issued: 04/16/1996
• Est. Priority Date: 02/24/1994
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Tominga, Shuuichi, Nakamura, Katsumi, Minato, Tadaharu, Shiozawa, Katsuomi
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): TRAN, MINH LOAN
• Application Number:
  US08/384,734
• Time in Patent Office: 434 Days
• Field of Search: 257/133, 257/135, 257/139, 257/153, 257/329, 257/330, 257/331, 257/341, 257/622, 257/637
• US Class Current: 257/135
• CPC Class Codes: H01L 29/41716 Cathode or anode electrodes for thyristors
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7455 produced by an insulated gate structure
• CPC Class Codes: H01L 29/749 with turn-on by field effect
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 148/011 Bipolar transistors
• CPC Class Codes: Y10S 148/05 Etch and refill
• CPC Class Codes: Y10S 148/133 Reflow oxides and glasses
• CPC Class Codes: Y10S 438/978 forming tapered edges on substrate or adjacent layers

Abstract

A semiconductor device including a layer formed without being affected by a stepped ground pattern and a method of fabricating the semiconductor device are disclosed. Cap portions (30) (insulating layers) formed over trenches (13) and covering doped polysilicon (5) have an inclined surface (26) which satisfies Y/X ≦5 where X is the length of the inclined surface (26) in a direction of the surface of a body (50) and Y is the height of the inclined surface (26) from the surface of the body (50). Formation of the insulating layers having the smooth inclined surface satisfying Y/X≦5 permits a first main electrode to be formed non-defectively without being affected by the ground pattern including the insulating layers.

Claims

1. A semiconductor device comprising:

a semiconductor body having first and second major surfaces;

a plurality of trench portions each selectively formed in the first major surface of said body to a predetermined depth;

a plurality of insulating films formed on respective inner walls of said plurality of trench portions;

a plurality of control electrode layers filled respectively in said plurality of trench portions, with said plurality of insulating films sandwiched between said control electrode layers and the inner walls of said trench portions;

a plurality of insulating layers formed respectively on said plurality of control electrode layers and projecting from the first major surface of said body;

a first main electrode formed over the first major surface of said body; and

a second main electrode formed on the second major surface of said body,

wherein a control voltage applied commonly to said plurality of control electrode layers controls current between said first and second main electrodes, and

wherein each of said plurality of insulating layers has an opposite surface, which is opposite the first surface, with rounded edges between an inclined surface, extending from the first major surface, and said opposite surface for preventing cavities from forming in the first main electrode during formation of the semiconductor device, and

the conditional expression;

Y/X≦

5 is satisfied where X is a length of said rounded edges in a direction of the first major surface of said body and Y is a height measured between a point where the rounded edges meet the opposite surface and the first major surface of said body.

2. The semiconductor device of claim 1, wherein

said plurality of trench portions are spaced a predetermined distance apart from each other, and

the conditional expression:

(W/H)≦

8 is satisfied where W is said predetermined distance and H is a height of said plurality of insulating layers from the first major surface of said body.

3. The semiconductor device of claim 1, wherein

said plurality of insulating films are integrally formed,

said plurality of control electrode layers are integrally formed, and

said plurality of insulating layers are integrally formed.

4. The semiconductor device of claim 1, wherein

each of said plurality of insulating layers includes:

a ground insulating layer formed on each of said control electrode layers; and

a major insulating layer formed on said ground insulating layer.

5. The semiconductor device of claim 1, wherein

each of said plurality of insulating layers includes:

a ground insulating layer formed on each of said control electrode layers;

a major insulating layer formed on said ground insulating layer; and

an auxiliary insulating layer formed on said major insulating layer.

6. The semiconductor device of claim 1,

wherein said body includes:

a first semiconductor layer having first and second major surfaces;

a first semiconductor region of a first conductivity type formed on the first major surface of said first semiconductor layer; and

a second semiconductor region of a second conductivity type formed on said first semiconductor region and having a surface, the second major surface of said first semiconductor layer being the second major surface of said body, the surface of said second semiconductor region being the first major surface of said body, and

wherein said plurality of trench portions are selectively formed so as to extend from the surface of said second semiconductor region through said second and first semiconductor regions.

7. The semiconductor device of claim 6, wherein

said first semiconductor layer includes:

a second semiconductor layer of the first conductivity type formed adjacent the second major surface of said first semiconductor layer; and

a third semiconductor layer formed adjacent the first major surface of said first semiconductor layer, said third semiconductor layer being intrinsic or of the second conductivity type.

8. The semiconductor device of claim 7,

wherein said third semiconductor layer includes:

a fourth semiconductor layer of the second conductivity type formed on said second semiconductor layer; and

a fifth semiconductor layer of the second conductivity type formed on said fourth semiconductor layer, said fourth semiconductor layer having an impurity concentration higher than that of said fifth semiconductor layer.

9. The semiconductor device of claim 7,

wherein said second semiconductor layer partially includes a third semiconductor region of the second conductivity type extending from a first major surface of said second semiconductor layer to a second major surface thereof.

10. The semiconductor device of claim 7,

wherein said second semiconductor layer partially includes a third semiconductor region of the second conductivity type extending from a first major surface of said second semiconductor layer to a second major surface thereof, and

wherein said third semiconductor layer includes:

a fourth semiconductor layer of the second conductivity type formed on said second semiconductor layer; and

a fifth semiconductor layer of the second conductivity type formed on said fourth semiconductor layer, said fourth semiconductor layer having an impurity concentration higher than that of said fifth semiconductor layer.

11. The semiconductor device of claim 6,

wherein said first semiconductor layer is of the second conductivity type.

12. The semiconductor device of claim 6, further comprising:

a third semiconductor region of the first conductivity type selectively formed in the surface of said second semiconductor region and having a surface, the surfaces of said third and second semiconductor regions being the first major surface of said body.

13. The semiconductor device of claim 12,

wherein said first semiconductor layer includes:

a second semiconductor layer of the first conductivity type formed adjacent the second major surface of said first semiconductor layer; and

a third semiconductor layer formed adjacent the first major surface of said first semiconductor layer, said third semiconductor layer being intrinsic or of the second conductivity type, and

wherein said second semiconductor layer partially includes a fourth semiconductor region of the second conductivity type extending from a first major surface of said second semiconductor layer to a second major surface thereof.

14. A semiconductor device comprising:

a semiconductor body having first and second major surfaces;

a plurality of trench portions each selectively formed from the first major surface of said body to a predetermined depth;

a plurality of insulating films formed over respective inner walls of said plurality of trench portions and part of the first major surface of said body;

a plurality of control electrode layers filled respectively in said plurality of trench portions, with said plurality of insulating films sandwiched between said control electrode layers and the inner walls of said trench portions, and extending over said part of the first major surface of said body, with said plurality of insulating films sandwiched between said control electrode layers and said body;

a plurality of insulating layers formed respectively on said plurality of control electrode layers in said plurality of trench portions and projecting from the first major surface of said body;

a first main electrode formed over the first major surface of said body; and

a second main electrode formed on the second major surface of said body,

wherein a control voltage applied commonly to said plurality of control electrode layers controls current between said first and second main electrodes, and

wherein

the conditional expression;

H2≧

H1 is satisfied where H1 is a height of said plurality of control electrode layers formed over said part of the first major surface of said body from the first major surface of said body and H2 is a height of said plurality of insulating layers over said plurality of trench portions from the first major surface of said body.

15. The semiconductor device of claim 14, wherein

said plurality of trench portions are spaced a predetermined distance apart from each other, and

the conditional expression:

(W/H2)≦

8 is satisfied where W is said predetermined distance.

16. The semiconductor device of claim 14, wherein

said plurality of insulating films are integrally formed,

said plurality of control electrode layers are integrally formed, and

said plurality of insulating layers are integrally formed.

17. The semiconductor device of claim 14, wherein

each of said plurality of insulating layers includes:

a ground insulating layer formed on each of said control electrode layers; and

a major insulating layer formed on said ground insulating layer.

18. The semiconductor device of claim 14, wherein, each of said plurality of insulating layers, includes:

a ground insulating layer formed on each of said control electrode layers;

a major insulating layer formed on said ground insulating layer.

19. The semiconductor device of claim 18, wherein

said plurality of insulating films are integrally formed,

said plurality of control electrode layers are integrally formed, and

said plurality of insulating layers are integrally formed.

20. The semiconductor device of claim 18, wherein

said plurality of trench portions are spaced a predetermined distance apart from each other, and

the conditional expression:

(W/H2)≦

8 is satisfied where W is said predetermined distance.

21. A semiconductor device comprising:

a semiconductor body having first and second major surfaces;

a plurality of trench portions each selectively formed from the first major surface of said body to a predetermined depth;

a plurality of insulating films formed over respective inner walls of said plurality of trench portions and part of the first major surface of said body;

a plurality of control electrode layers filled respectively in said plurality of trench portions, with said plurality of insulating films sandwiched between said control electrode layers and the inner walls of said trench portions, and extending over said part of the first major surface of said body, with said plurality of insulating films sandwiched between said control electrode layers and said body;

a plurality of insulating layers formed respectively on said plurality of control electrode layers in said plurality of trench portions and projecting from the first major surface of said body;

a first main electrode formed over the first major surface of said body; and

a second main electrode formed on the second major surface of said body,

wherein a control voltage applied commonly to said plurality of control electrode layers controls current between said first and second main electrodes, and

wherein each of said plurality of insulating layers over said plurality of trench portions has a smooth inclined surface from top to bottom, and

the conditional expression;

H2≧

H1 and

the conditional expression;

Y/X≦

5 are both satisfied where X is a length of said inclined surface in a direction of the first major surface of said body, Y is a height of said inclined surface from the first major surface of said body, Y is a height of said plurality of control electrode layers formed over said part of the first major surface of said body from the first major surface of said body, and H2 is a height of said plurality of insulating layers over said plurality of trench portions from the first major surface of said body.

22. The semiconductor device of claim 21, wherein

each of said plurality of insulating layers includes:

a ground insulating layer formed on each of said control electrode layers; and

a major insulating layer formed on said ground insulating layer.

23. The semiconductor device of claim 21, wherein

each of said plurality of insulating layers includes:

a ground insulating layer formed on each of said control electrode layers;

a major insulating layer formed on said ground insulating layer; and

an auxiliary insulating layer formed on said major insulating layer.

24. A semiconductor device comprising:

a body having first and second major surfaces and including an upper layer portion adjacent the first major surface and a lower layer portion adjacent the second major surface, at least said upper layer portion being made of a semiconductor of a first conductivity type;

a plurality of first semiconductor regions of a second conductivity type selectively formed in said upper layer portion of said body;

a plurality of second semiconductor regions of the first conductivity type selectively formed in respective surfaces of said plurality of first semiconductor regions;

a plurality of insulating films each formed on one of said first semiconductor regions between said upper layer portion of said body and said second semiconductor regions;

a plurality of control electrodes formed respectively on said plurality of insulating films;

a plurality of insulating layers for covering said plurality of insulating films and said plurality of control electrodes, respectively;

a first main electrode formed over the first major surface of said body; and

a second main electrode formed on the second major surface of said body,

wherein a control voltage applied commonly to said plurality of control electrodes controls current between said first and second main electrodes, and

wherein each of said plurality of insulating layers has an opposite surface, which is opposite the first surface, with rounded edges between an inclined surface, extending from the first major surface, and said opposite surface for preventing cavities from forming in the first main electrode during formation of the semiconductor device, and

the conditional expression;

Y/X≦

5 is satisfied where X is a length of said rounded edges in a direction of the first major surface of said body and Y is a height measured between a point where the rounded edges meet the opposite surface and the first major surface of said body;

wherein said plurality of control electrodes are spaced a predetermined distance apart from each other, and

the conditional expression (W/H)≦

8 is satisfied where W is said predetermined distance and H is a heiqht of said plurality of insulating layers from the first major surface of said body.

25. The semiconductor device of claim 24,

wherein said lower layer portion of said body is of the second conductivity type.