Porous silicon trench and capacitor structures

• US 5,508,542 A
• Filed: 10/28/1994
• Issued: 04/16/1996
• Est. Priority Date: 10/28/1994
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Geiss, Peter J., Kenney, Donald M.
• Primary Examiner(s): Limanek, Robert P.
• Application Number:
  US08/330,652
• Time in Patent Office: 536 Days
• Field of Search: 257/301, 257/305, 257/309
• US Class Current: 257/301
• CPC Class Codes: H01L 28/82 with an enlarged surface, e.g. formed by texturisation
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 29/945 Trench capacitors
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: Y10S 438/96 Porous semiconductor
• CPC Class Codes: Y10S 977/721 On a silicon substrate
• CPC Class Codes: Y10S 977/888 Shaping or removal of materials, e.g. etching
• CPC Class Codes: Y10S 977/899 Electrolytic

Abstract

The invention provides a capacitor structure utilizing porous silicon as a first plate of the capacitor structure, thereby greatly increasing the surface area available for the capacitor and thereby the capacitance attainable. The invention also provides a trench structure having a porous silicon region surrounding the sidewalks thereof. Such a trench can then be utilized to totem a capacitor according to the subject invention. Methods of producing the capacitor and trench structures according to the subject invention are also provided. Porous silicon is produced utilizing electrolytic anodic etching.

Claims

1. A semiconductor capacitor structure comprising:

a semiconductor substrate comprised of monocrystalline silicon, said substrate comprising an upper portion and a lower portion, said upper portion having a low conductivity and said lower portion having a high conductivity, and having an area of porous silicon confined essentially to said lower portion of said substrate;

a conformal layer of a dielectric material overlying said area of porous silicon; and

a conformal layer of silicon overlying said layer of dielectric material;

wherein said area of porous silicon forms a first plate of a capacitor structure and said conformal layer of silicon forms a second plate of said capacitor structure, said first plate separated from said second plate by said layer of dielectric material.

2. The semiconductor capacitor structure of claim 1 wherein said lower portion of said semiconductor substrate of monocrystalline silicon comprises p+ monocrystalline silicon.

3. The semiconductor capacitor structure of claim 1 wherein said conformal layer of dielectric material comprises a multi-layer dielectric material.

4. The semiconductor capacitor structure of claim 3 wherein said multi-layer dielectric material is selected from the group consisting of oxide/nitride, nitride/oxide, and oxide/nitride/oxide.

5. The semiconductor capacitor structure of claim 1 wherein said area of porous silicon comprises electrolytically anodized porous silicon.

6. The semiconductor capacitor structure of claim 1 wherein said conformal layer of silicon comprises polysilicon.

31. The semiconductor capacitor structure of claim 1 wherein said upper portion of said semiconductor substrate of monocrystalline silicon comprises n-doped monocrystalline silicon.

32. The semiconductor capacitor structure of claim 1 wherein said upper portion of said semiconductor substrate of monocrystalline silicon comprises p-monocrystalline silicon.

7. A semiconductor trench structure comprising:

a semiconductor substrate of monocrystalline silicon, said substrate comprising an upper portion and a lower portion, said upper portion having a low conductivity and said lower portion having a high conductivity;

a trench formed in said semiconductor substrate, said trench having side walls and a bottom surface; and

a porous silicon region surrounding said side walls and said bottom surface of said trench and confined essentially to said lower portion of said substrate.

8. The semiconductor trench structure of claim 7 wherein said lower portion of said semiconductor substrate comprises p+ monocrystalline silicon.

9. The semiconductor trench structure of claim 7 wherein said upper portion comprises p- silicon.

10. The semiconductor trench structure of claim 7 wherein said upper portion comprises n-doped monocrystalline silicon.

11. The semiconductor trench structure of claim 7 wherein said porous silicon region comprises electrolytically anodized porous silicon.

12. The semiconductor trench structure of claim 7 further comprising:

a conformal layer of a dielectric material overlying said porous silicon region; and

a conformal layer of silicon overlying said layer of dielectric material;

wherein said porous silicon region forms a first plate of a capacitor structure and said conformal layer of silicon forms a second plate of said capacitor structure, said first plate separated from said second plate by said conformal layer of dielectric material.

13. The semiconductor trench structure of claim 12 wherein said dielectric material comprises a multi-layer dielectric material.

14. The semiconductor trench structure of claim 12 wherein said dielectric material is selected from the group consisting of nitride, oxide, oxide/nitride, nitride/oxide, and oxide/nitride/oxide.

15. The semiconductor trench structure of claim 12 wherein said conformal layer of silicon comprises polysilicon.

33. The semiconductor trench structure of claim 11, wherein said electrolytically anodized porous silicon region is formed subsequent to the formation of said upper portion of said semiconductor substrate.

16. A semiconductor trench structure comprising:

a semiconductor substrate of monocrystalline silicon;

a first trench formed in said semiconductor substrate, said first trench having side walls and a bottom surface;

a first porous silicon region surrounding said side walls and said bottom surface of said first trench;

a second trench formed in said semiconductor substrate adjacent said first trench, said second trench having side walls and a bottom surface;

a second porous silicon region surrounding said side walls and said bottom surface of said second trench;

an area of said semiconductor substrate of silicon separating said first porous silicon region from said second porous silicon region;

wherein said first porous region of said first trench and said second porous region of said second trench are formed contemporaneously by a self-limiting anodizing process.

17. The semiconductor trench structure of claim 16 wherein said semiconductor substrate or monocrystalline silicon comprises p+ monocrystalline silicon.

18. The semiconductor trench structure of claim 16 wherein said semiconductor substrate of monocrystalline silicon has an upper portion and a lower portion, said first trench and said second trench each formed in said semiconductor substrate of monocrystalline silicon through said upper portion and into said lower portion.

19. The semiconductor trench structure of claim 18 wherein said upper portion comprises p- monocrystalline silicon.

20. The semiconductor trench structure of claim 18 wherein said upper portion comprises n-doped monocrystalline silicon.

21. The semiconductor trench structure of claim 18 wherein said lower portion comprises p+ monocrystalline silicon.

22. The semiconductor trench structure of claim 18 wherein said first porous silicon region surrounds said side walls of said first trench in said lower portion of said semiconductor substrate of monocrystalline silicon.

23. The semiconductor trench structure of claim 18 wherein said second porous silicon region surrounds said side walls of said second trench in said lower portion of said semiconductor substrate of monocrystalline silicon.

24. The semiconductor trench structure of claim 16 wherein said first porous silicon region comprises electrolytically anodized porous silicon.

25. The semiconductor trench structure of claim 16 wherein said second porous silicon region comprises electrolytically anodized porous silicon.

26. The semiconductor trench structure of claim 16 further comprising:

a conformal layer of a dielectric material overlying said first porous silicon region;

a conformal layer of silicon overlying said conformal layer of dielectric material;

said conformal layer of a dielectric material overlying said second porous silicon region; and

wherein said first porous silicon region forms a first plate of a first capacitor structure and said conformal layer of silicon forms a second plate of said first capacitor structure, said first plate separated from said second plate by said conformal layer of a dielectric material,

and wherein said second porous silicon region forms a first plate of a second capacitor structure and said conformal layer of silicon forms a second plate of said second capacitor structure, said first plate of said second capacitor structure separated from said second plate of said second capacitor structure by said conformal layer of a dielectric material.

27. The semiconductor trench structure of claim 26 wherein said conformal layer of dielectric material comprises a multi-layer dielectric material.

28. The semiconductor trench structure of claim 26 wherein each of said first conformal layer of dielectric material and said second conformal layer of dielectric material comprise a dielectric material selected from the group consisting of nitride, oxide, oxide/nitride, nitride/oxide, and oxide/nitride/oxide.

29. The semiconductor trench structure of claim 26 wherein said conformal layer or silicon comprises polysilicon.

30. A semiconductor trench capacitor structure comprising:

a semiconductor substrate of monocrystalline silicon, said substrate comprising an upper substrate portion and a lower substrate portion, said upper substrate portion having a low conductivity and said lower substrate portion having a high conductivity;

a trench formed in said semiconductor substrate through said upper substrate portion and said lower substrate portion, said trench having a bottom wall and a side wall having an upper side wall portion and a lower side wall portion;

a porous silicon region surrounding said lower side wall portion and said bottom wall of said trench and confined essentially to said lower substrate portion of said substrate;

a dielectric layer conformally formed overlying said porous silicon region;

a side wall-defined isolating layer formed within an upper portion of said trench and extending from at least some of said upper side wall portion toward a center of said trench to provide isolation so as to prevent parasitic device formation with an active semiconductor region abutting said trench, said isolating layer being formed of an electrical insulation material and being substantially thicker than said insulating layer and thinner than one-half of a width of said trench; and

a conductive electrode formed of a conductive material conformally overlying said dielectric layer and deposited within a remainder of said trench.